dyn_inst.cc (10934:5af8f40d8f2c) dyn_inst.cc (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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152 if (reg == TheISA::ZeroReg) {
153 os << 'z';
154 } else {
155 os << 'r' << static_cast<unsigned int>(reg);
156 }
157 break;
158 case CCRegClass:
159 os << 'c' << static_cast<unsigned int>(reg - TheISA::CC_Reg_Base);
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 143 unchanged lines hidden (view full) ---

152 if (reg == TheISA::ZeroReg) {
153 os << 'z';
154 } else {
155 os << 'r' << static_cast<unsigned int>(reg);
156 }
157 break;
158 case CCRegClass:
159 os << 'c' << static_cast<unsigned int>(reg - TheISA::CC_Reg_Base);
160 case VectorRegClass:
161 os << 'v' << static_cast<unsigned int>(reg - TheISA::Vector_Reg_Base);
162 }
163}
164
165void
166MinorDynInst::minorTraceInst(const Named &named_object) const
167{
168 if (isFault()) {
169 MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",

--- 60 unchanged lines hidden --- 		160 }
161}
162
163void
164MinorDynInst::minorTraceInst(const Named &named_object) const
165{
166 if (isFault()) {
167 MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",

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