1/*
2 * Copyright (c) 2013-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/dyn_inst.hh"
41
42#include <iomanip>
43#include <sstream>
44
45#include "arch/isa.hh"
46#include "arch/registers.hh"
47#include "cpu/base.hh"
48#include "cpu/minor/trace.hh"
49#include "cpu/reg_class.hh"
50#include "debug/MinorExecute.hh"
51#include "enums/OpClass.hh"
52
53namespace Minor
54{
55
56const InstSeqNum InstId::firstStreamSeqNum;
57const InstSeqNum InstId::firstPredictionSeqNum;
58const InstSeqNum InstId::firstLineSeqNum;
59const InstSeqNum InstId::firstFetchSeqNum;
60const InstSeqNum InstId::firstExecSeqNum;
61
62std::ostream &
63operator <<(std::ostream &os, const InstId &id)
64{
65 os << id.threadId << '/' << id.streamSeqNum << '.'
66 << id.predictionSeqNum << '/' << id.lineSeqNum;
67
68 /* Not all structures have fetch and exec sequence numbers */
69 if (id.fetchSeqNum != 0) {
70 os << '/' << id.fetchSeqNum;
71 if (id.execSeqNum != 0)
72 os << '.' << id.execSeqNum;
73 }
74
75 return os;
76}
77
78MinorDynInstPtr MinorDynInst::bubbleInst = NULL;
79
80void
81MinorDynInst::init()
82{
83 if (!bubbleInst) {
84 bubbleInst = new MinorDynInst();
85 assert(bubbleInst->isBubble());
86 /* Make bubbleInst immortal */
87 bubbleInst->incref();
88 }
89}
90
91bool
92MinorDynInst::isLastOpInInst() const
93{
94 assert(staticInst);
95 return !(staticInst->isMicroop() && !staticInst->isLastMicroop());
96}
97
98bool
99MinorDynInst::isNoCostInst() const
100{
101 return isInst() && staticInst->opClass() == No_OpClass;
102}
103
104void
105MinorDynInst::reportData(std::ostream &os) const
106{
107 if (isBubble())
108 os << "-";
109 else if (isFault())
110 os << "F;" << id;
111 else
112 os << id;
113}
114
115std::ostream &
116operator <<(std::ostream &os, const MinorDynInst &inst)
117{
118 os << inst.id << " pc: 0x"
119 << std::hex << inst.pc.instAddr() << std::dec << " (";
120
121 if (inst.isFault())
122 os << "fault: \"" << inst.fault->name() << '"';
123 else if (inst.staticInst)
124 os << inst.staticInst->getName();
125 else
126 os << "bubble";
127
128 os << ')';
129
130 return os;
131}
132
133/** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer,
134 * float, misc and zero registers given an 'architectural register number' */
135static void
136printRegName(std::ostream &os, const RegId& reg)
137{
138 switch (reg.classValue())
139 {
140 case MiscRegClass:
141 {
142 RegIndex misc_reg = reg.index();
143
144 /* This is an ugly test because not all archs. have miscRegName */
145#if THE_ISA == ARM_ISA
146 os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
147 ')';
148#else
149 os << 'n' << misc_reg;
150#endif
151 }
152 break;
153 case FloatRegClass:
154 os << 'f' << static_cast<unsigned int>(reg.index());
155 break;
156 case VecRegClass:
157 os << 'v' << static_cast<unsigned int>(reg.index());
158 break;
159 case VecElemClass:
160 os << 'v' << static_cast<unsigned int>(reg.index()) << '[' <<
161 static_cast<unsigned int>(reg.elemIndex()) << ']';
162 break;
163 case IntRegClass:
164 if (reg.isZeroReg()) {
165 os << 'z';
166 } else {
167 os << 'r' << static_cast<unsigned int>(reg.index());
168 }
169 break;
170 case CCRegClass:
171 os << 'c' << static_cast<unsigned int>(reg.index());
| 1/*
2 * Copyright (c) 2013-2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/dyn_inst.hh"
41
42#include <iomanip>
43#include <sstream>
44
45#include "arch/isa.hh"
46#include "arch/registers.hh"
47#include "cpu/base.hh"
48#include "cpu/minor/trace.hh"
49#include "cpu/reg_class.hh"
50#include "debug/MinorExecute.hh"
51#include "enums/OpClass.hh"
52
53namespace Minor
54{
55
56const InstSeqNum InstId::firstStreamSeqNum;
57const InstSeqNum InstId::firstPredictionSeqNum;
58const InstSeqNum InstId::firstLineSeqNum;
59const InstSeqNum InstId::firstFetchSeqNum;
60const InstSeqNum InstId::firstExecSeqNum;
61
62std::ostream &
63operator <<(std::ostream &os, const InstId &id)
64{
65 os << id.threadId << '/' << id.streamSeqNum << '.'
66 << id.predictionSeqNum << '/' << id.lineSeqNum;
67
68 /* Not all structures have fetch and exec sequence numbers */
69 if (id.fetchSeqNum != 0) {
70 os << '/' << id.fetchSeqNum;
71 if (id.execSeqNum != 0)
72 os << '.' << id.execSeqNum;
73 }
74
75 return os;
76}
77
78MinorDynInstPtr MinorDynInst::bubbleInst = NULL;
79
80void
81MinorDynInst::init()
82{
83 if (!bubbleInst) {
84 bubbleInst = new MinorDynInst();
85 assert(bubbleInst->isBubble());
86 /* Make bubbleInst immortal */
87 bubbleInst->incref();
88 }
89}
90
91bool
92MinorDynInst::isLastOpInInst() const
93{
94 assert(staticInst);
95 return !(staticInst->isMicroop() && !staticInst->isLastMicroop());
96}
97
98bool
99MinorDynInst::isNoCostInst() const
100{
101 return isInst() && staticInst->opClass() == No_OpClass;
102}
103
104void
105MinorDynInst::reportData(std::ostream &os) const
106{
107 if (isBubble())
108 os << "-";
109 else if (isFault())
110 os << "F;" << id;
111 else
112 os << id;
113}
114
115std::ostream &
116operator <<(std::ostream &os, const MinorDynInst &inst)
117{
118 os << inst.id << " pc: 0x"
119 << std::hex << inst.pc.instAddr() << std::dec << " (";
120
121 if (inst.isFault())
122 os << "fault: \"" << inst.fault->name() << '"';
123 else if (inst.staticInst)
124 os << inst.staticInst->getName();
125 else
126 os << "bubble";
127
128 os << ')';
129
130 return os;
131}
132
133/** Print a register in the form r<n>, f<n>, m<n>(<name>), z for integer,
134 * float, misc and zero registers given an 'architectural register number' */
135static void
136printRegName(std::ostream &os, const RegId& reg)
137{
138 switch (reg.classValue())
139 {
140 case MiscRegClass:
141 {
142 RegIndex misc_reg = reg.index();
143
144 /* This is an ugly test because not all archs. have miscRegName */
145#if THE_ISA == ARM_ISA
146 os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] <<
147 ')';
148#else
149 os << 'n' << misc_reg;
150#endif
151 }
152 break;
153 case FloatRegClass:
154 os << 'f' << static_cast<unsigned int>(reg.index());
155 break;
156 case VecRegClass:
157 os << 'v' << static_cast<unsigned int>(reg.index());
158 break;
159 case VecElemClass:
160 os << 'v' << static_cast<unsigned int>(reg.index()) << '[' <<
161 static_cast<unsigned int>(reg.elemIndex()) << ']';
162 break;
163 case IntRegClass:
164 if (reg.isZeroReg()) {
165 os << 'z';
166 } else {
167 os << 'r' << static_cast<unsigned int>(reg.index());
168 }
169 break;
170 case CCRegClass:
171 os << 'c' << static_cast<unsigned int>(reg.index());
|
172 default:
173 panic("Unknown register class: %d", (int)reg.classValue());
174 }
175}
176
177void
178MinorDynInst::minorTraceInst(const Named &named_object) const
179{
180 if (isFault()) {
181 MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
182 id, pc.instAddr(), fault->name());
183 } else {
184 unsigned int num_src_regs = staticInst->numSrcRegs();
185 unsigned int num_dest_regs = staticInst->numDestRegs();
186
187 std::ostringstream regs_str;
188
189 /* Format lists of src and dest registers for microops and
190 * 'full' instructions */
191 if (!staticInst->isMacroop()) {
192 regs_str << " srcRegs=";
193
194 unsigned int src_reg = 0;
195 while (src_reg < num_src_regs) {
196 printRegName(regs_str, staticInst->srcRegIdx(src_reg));
197
198 src_reg++;
199 if (src_reg != num_src_regs)
200 regs_str << ',';
201 }
202
203 regs_str << " destRegs=";
204
205 unsigned int dest_reg = 0;
206 while (dest_reg < num_dest_regs) {
207 printRegName(regs_str, staticInst->destRegIdx(dest_reg));
208
209 dest_reg++;
210 if (dest_reg != num_dest_regs)
211 regs_str << ',';
212 }
213
214#if THE_ISA == ARM_ISA
215 regs_str << " extMachInst=" << std::hex << std::setw(16)
216 << std::setfill('0') << staticInst->machInst << std::dec;
217#endif
218 }
219
220 std::ostringstream flags;
221 staticInst->printFlags(flags, " ");
222
223 MINORINST(&named_object, "id=%s addr=0x%x inst=\"%s\" class=%s"
224 " flags=\"%s\"%s%s\n",
225 id, pc.instAddr(),
226 (staticInst->opClass() == No_OpClass ?
227 "(invalid)" : staticInst->disassemble(0,NULL)),
228 Enums::OpClassStrings[staticInst->opClass()],
229 flags.str(),
230 regs_str.str(),
231 (predictedTaken ? " predictedTaken" : ""));
232 }
233}
234
235MinorDynInst::~MinorDynInst()
236{
237 if (traceData)
238 delete traceData;
239}
240
241}
| 173 default:
174 panic("Unknown register class: %d", (int)reg.classValue());
175 }
176}
177
178void
179MinorDynInst::minorTraceInst(const Named &named_object) const
180{
181 if (isFault()) {
182 MINORINST(&named_object, "id=F;%s addr=0x%x fault=\"%s\"\n",
183 id, pc.instAddr(), fault->name());
184 } else {
185 unsigned int num_src_regs = staticInst->numSrcRegs();
186 unsigned int num_dest_regs = staticInst->numDestRegs();
187
188 std::ostringstream regs_str;
189
190 /* Format lists of src and dest registers for microops and
191 * 'full' instructions */
192 if (!staticInst->isMacroop()) {
193 regs_str << " srcRegs=";
194
195 unsigned int src_reg = 0;
196 while (src_reg < num_src_regs) {
197 printRegName(regs_str, staticInst->srcRegIdx(src_reg));
198
199 src_reg++;
200 if (src_reg != num_src_regs)
201 regs_str << ',';
202 }
203
204 regs_str << " destRegs=";
205
206 unsigned int dest_reg = 0;
207 while (dest_reg < num_dest_regs) {
208 printRegName(regs_str, staticInst->destRegIdx(dest_reg));
209
210 dest_reg++;
211 if (dest_reg != num_dest_regs)
212 regs_str << ',';
213 }
214
215#if THE_ISA == ARM_ISA
216 regs_str << " extMachInst=" << std::hex << std::setw(16)
217 << std::setfill('0') << staticInst->machInst << std::dec;
218#endif
219 }
220
221 std::ostringstream flags;
222 staticInst->printFlags(flags, " ");
223
224 MINORINST(&named_object, "id=%s addr=0x%x inst=\"%s\" class=%s"
225 " flags=\"%s\"%s%s\n",
226 id, pc.instAddr(),
227 (staticInst->opClass() == No_OpClass ?
228 "(invalid)" : staticInst->disassemble(0,NULL)),
229 Enums::OpClassStrings[staticInst->opClass()],
230 flags.str(),
231 regs_str.str(),
232 (predictedTaken ? " predictedTaken" : ""));
233 }
234}
235
236MinorDynInst::~MinorDynInst()
237{
238 if (traceData)
239 delete traceData;
240}
241
242}
|