decode.hh (10259:ebb376f73dd2) | decode.hh (11567:560d7fbbddd1) |
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1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 MinorCPU &cpu; 67 68 /** Input port carrying macro instructions from Fetch2 */ 69 Latch<ForwardInstData>::Output inp; 70 /** Output port carrying micro-op decomposed instructions to Execute */ 71 Latch<ForwardInstData>::Input out; 72 73 /** Interface to reserve space in the next stage */ | 1/* 2 * Copyright (c) 2013-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 57 unchanged lines hidden (view full) --- 66 MinorCPU &cpu; 67 68 /** Input port carrying macro instructions from Fetch2 */ 69 Latch<ForwardInstData>::Output inp; 70 /** Output port carrying micro-op decomposed instructions to Execute */ 71 Latch<ForwardInstData>::Input out; 72 73 /** Interface to reserve space in the next stage */ |
74 Reservable &nextStageReserve; | 74 std::vector<InputBuffer<ForwardInstData>> &nextStageReserve; |
75 76 /** Width of output of this stage/input of next in instructions */ 77 unsigned int outputWidth; 78 79 /** If true, more than one input word can be processed each cycle if 80 * there is room in the output to contain its processed data */ 81 bool processMoreThanOneInput; 82 83 public: 84 /* Public for Pipeline to be able to pass it to Fetch2 */ | 75 76 /** Width of output of this stage/input of next in instructions */ 77 unsigned int outputWidth; 78 79 /** If true, more than one input word can be processed each cycle if 80 * there is room in the output to contain its processed data */ 81 bool processMoreThanOneInput; 82 83 public: 84 /* Public for Pipeline to be able to pass it to Fetch2 */ |
85 InputBuffer<ForwardInstData> inputBuffer; | 85 std::vector<InputBuffer<ForwardInstData>> inputBuffer; |
86 87 protected: 88 /** Data members after this line are cycle-to-cycle state */ 89 | 86 87 protected: 88 /** Data members after this line are cycle-to-cycle state */ 89 |
90 /** Index into the inputBuffer's head marking the start of unhandled 91 * instructions */ 92 unsigned int inputIndex; | 90 struct DecodeThreadInfo { |
93 | 91 |
94 /** True when we're in the process of decomposing a micro-op and 95 * microopPC will be valid. This is only the case when there isn't 96 * sufficient space in Executes input buffer to take the whole of a 97 * decomposed instruction and some of that instructions micro-ops must 98 * be generated in a later cycle */ 99 bool inMacroop; 100 TheISA::PCState microopPC; | 92 /** Default Constructor */ 93 DecodeThreadInfo() : 94 inputIndex(0), 95 inMacroop(false), 96 execSeqNum(InstId::firstExecSeqNum), 97 blocked(false) 98 { } |
101 | 99 |
102 /** Source of execSeqNums to number instructions. */ 103 InstSeqNum execSeqNum; | 100 DecodeThreadInfo(const DecodeThreadInfo& other) : 101 inputIndex(other.inputIndex), 102 inMacroop(other.inMacroop), 103 execSeqNum(other.execSeqNum), 104 blocked(other.blocked) 105 { } |
104 | 106 |
105 /** Blocked indication for report */ 106 bool blocked; | |
107 | 107 |
108 /** Index into the inputBuffer's head marking the start of unhandled 109 * instructions */ 110 unsigned int inputIndex; 111 112 /** True when we're in the process of decomposing a micro-op and 113 * microopPC will be valid. This is only the case when there isn't 114 * sufficient space in Executes input buffer to take the whole of a 115 * decomposed instruction and some of that instructions micro-ops must 116 * be generated in a later cycle */ 117 bool inMacroop; 118 TheISA::PCState microopPC; 119 120 /** Source of execSeqNums to number instructions. */ 121 InstSeqNum execSeqNum; 122 123 /** Blocked indication for report */ 124 bool blocked; 125 }; 126 127 std::vector<DecodeThreadInfo> decodeInfo; 128 ThreadID threadPriority; 129 |
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108 protected: 109 /** Get a piece of data to work on, or 0 if there is no data. */ | 130 protected: 131 /** Get a piece of data to work on, or 0 if there is no data. */ |
110 const ForwardInstData *getInput(); | 132 const ForwardInstData *getInput(ThreadID tid); |
111 112 /** Pop an element off the input buffer, if there are any */ | 133 134 /** Pop an element off the input buffer, if there are any */ |
113 void popInput(); | 135 void popInput(ThreadID tid); |
114 | 136 |
137 /** Use the current threading policy to determine the next thread to 138 * decode from. */ 139 ThreadID getScheduledThread(); |
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115 public: 116 Decode(const std::string &name, 117 MinorCPU &cpu_, 118 MinorCPUParams ¶ms, 119 Latch<ForwardInstData>::Output inp_, 120 Latch<ForwardInstData>::Input out_, | 140 public: 141 Decode(const std::string &name, 142 MinorCPU &cpu_, 143 MinorCPUParams ¶ms, 144 Latch<ForwardInstData>::Output inp_, 145 Latch<ForwardInstData>::Input out_, |
121 Reservable &next_stage_input_buffer); | 146 std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer); |
122 123 public: 124 /** Pass on input/buffer data to the output if you can */ 125 void evaluate(); 126 127 void minorTrace() const; 128 129 /** Is this stage drained? For Decoed, draining is initiated by 130 * Execute halting Fetch1 causing Fetch2 to naturally drain 131 * into Decode and on to Execute which is responsible for 132 * actually killing instructions */ 133 bool isDrained(); 134}; 135 136} 137 138#endif /* __CPU_MINOR_DECODE_HH__ */ | 147 148 public: 149 /** Pass on input/buffer data to the output if you can */ 150 void evaluate(); 151 152 void minorTrace() const; 153 154 /** Is this stage drained? For Decoed, draining is initiated by 155 * Execute halting Fetch1 causing Fetch2 to naturally drain 156 * into Decode and on to Execute which is responsible for 157 * actually killing instructions */ 158 bool isDrained(); 159}; 160 161} 162 163#endif /* __CPU_MINOR_DECODE_HH__ */ |