cpu.hh (11168:f98eb2da15a4) cpu.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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109
110 protected:
111 /** Snooping a coherence request, do nothing. */
112 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
113 };
114
115 protected:
116 /** Return a reference to the data port. */
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 100 unchanged lines hidden (view full) ---

109
110 protected:
111 /** Snooping a coherence request, do nothing. */
112 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
113 };
114
115 protected:
116 /** Return a reference to the data port. */
117 MasterPort &getDataPort();
117 MasterPort &getDataPort() override;
118
119 /** Return a reference to the instruction port. */
118
119 /** Return a reference to the instruction port. */
120 MasterPort &getInstPort();
120 MasterPort &getInstPort() override;
121
122 public:
123 MinorCPU(MinorCPUParams *params);
124
125 ~MinorCPU();
126
127 public:
128 /** Starting, waking and initialisation */
121
122 public:
123 MinorCPU(MinorCPUParams *params);
124
125 ~MinorCPU();
126
127 public:
128 /** Starting, waking and initialisation */
129 void init();
130 void startup();
129 void init() override;
130 void startup() override;
131 void wakeup(ThreadID tid) override;
132
133 Addr dbg_vtophys(Addr addr);
134
135 /** Processor-specific statistics */
136 Minor::MinorStats stats;
137
138 /** Stats interface from SimObject (by way of BaseCPU) */
131 void wakeup(ThreadID tid) override;
132
133 Addr dbg_vtophys(Addr addr);
134
135 /** Processor-specific statistics */
136 Minor::MinorStats stats;
137
138 /** Stats interface from SimObject (by way of BaseCPU) */
139 void regStats();
139 void regStats() override;
140
141 /** Simple inst count interface from BaseCPU */
140
141 /** Simple inst count interface from BaseCPU */
142 Counter totalInsts() const;
143 Counter totalOps() const;
142 Counter totalInsts() const override;
143 Counter totalOps() const override;
144
145 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
146 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
147
148 /** Serialize pipeline data */
144
145 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
146 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
147
148 /** Serialize pipeline data */
149 void serialize(CheckpointOut &cp) const;
150 void unserialize(CheckpointIn &cp);
149 void serialize(CheckpointOut &cp) const override;
150 void unserialize(CheckpointIn &cp) override;
151
152 /** Drain interface */
153 DrainState drain() override;
154 void drainResume() override;
155 /** Signal from Pipeline that MinorCPU should signal that a drain
156 * is complete and set its drainState */
157 void signalDrainDone();
151
152 /** Drain interface */
153 DrainState drain() override;
154 void drainResume() override;
155 /** Signal from Pipeline that MinorCPU should signal that a drain
156 * is complete and set its drainState */
157 void signalDrainDone();
158 void memWriteback();
158 void memWriteback() override;
159
160 /** Switching interface from BaseCPU */
159
160 /** Switching interface from BaseCPU */
161 void switchOut();
162 void takeOverFrom(BaseCPU *old_cpu);
161 void switchOut() override;
162 void takeOverFrom(BaseCPU *old_cpu) override;
163
164 /** Thread activation interface from BaseCPU. */
163
164 /** Thread activation interface from BaseCPU. */
165 void activateContext(ThreadID thread_id);
166 void suspendContext(ThreadID thread_id);
165 void activateContext(ThreadID thread_id) override;
166 void suspendContext(ThreadID thread_id) override;
167
168 /** Interface for stages to signal that they have become active after
169 * a callback or eventq event where the pipeline itself may have
170 * already been idled. The stage argument should be from the
171 * enumeration Pipeline::StageId */
172 void wakeupOnEvent(unsigned int stage_id);
173};
174
175#endif /* __CPU_MINOR_CPU_HH__ */
167
168 /** Interface for stages to signal that they have become active after
169 * a callback or eventq event where the pipeline itself may have
170 * already been idled. The stage argument should be from the
171 * enumeration Pipeline::StageId */
172 void wakeupOnEvent(unsigned int stage_id);
173};
174
175#endif /* __CPU_MINOR_CPU_HH__ */