cpu.hh (11151:ca4ea9b5c052) cpu.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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123 MinorCPU(MinorCPUParams *params);
124
125 ~MinorCPU();
126
127 public:
128 /** Starting, waking and initialisation */
129 void init();
130 void startup();
1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 114 unchanged lines hidden (view full) ---

123 MinorCPU(MinorCPUParams *params);
124
125 ~MinorCPU();
126
127 public:
128 /** Starting, waking and initialisation */
129 void init();
130 void startup();
131 void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
131 void wakeup(ThreadID tid) override;
132
133 Addr dbg_vtophys(Addr addr);
134
135 /** Processor-specific statistics */
136 Minor::MinorStats stats;
137
138 /** Stats interface from SimObject (by way of BaseCPU) */
139 void regStats();
140
141 /** Simple inst count interface from BaseCPU */
142 Counter totalInsts() const;
143 Counter totalOps() const;
144
132
133 Addr dbg_vtophys(Addr addr);
134
135 /** Processor-specific statistics */
136 Minor::MinorStats stats;
137
138 /** Stats interface from SimObject (by way of BaseCPU) */
139 void regStats();
140
141 /** Simple inst count interface from BaseCPU */
142 Counter totalInsts() const;
143 Counter totalOps() const;
144
145 void serializeThread(CheckpointOut &cp,
146 ThreadID tid) const M5_ATTR_OVERRIDE;
147 void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
145 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
146 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
148
149 /** Serialize pipeline data */
150 void serialize(CheckpointOut &cp) const;
151 void unserialize(CheckpointIn &cp);
152
153 /** Drain interface */
147
148 /** Serialize pipeline data */
149 void serialize(CheckpointOut &cp) const;
150 void unserialize(CheckpointIn &cp);
151
152 /** Drain interface */
154 DrainState drain() M5_ATTR_OVERRIDE;
155 void drainResume() M5_ATTR_OVERRIDE;
153 DrainState drain() override;
154 void drainResume() override;
156 /** Signal from Pipeline that MinorCPU should signal that a drain
157 * is complete and set its drainState */
158 void signalDrainDone();
159 void memWriteback();
160
161 /** Switching interface from BaseCPU */
162 void switchOut();
163 void takeOverFrom(BaseCPU *old_cpu);

--- 13 unchanged lines hidden --- 		155 /** Signal from Pipeline that MinorCPU should signal that a drain
156 * is complete and set its drainState */
157 void signalDrainDone();
158 void memWriteback();
159
160 /** Switching interface from BaseCPU */
161 void switchOut();
162 void takeOverFrom(BaseCPU *old_cpu);

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