cpu.hh (10259:ebb376f73dd2) | cpu.hh (10407:a9023811bf9e) |
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1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 * This pipeline is carried in the MinorCPU::pipeline object. 74 * The exec_context interface is not carried by MinorCPU but by 75 * Minor::ExecContext objects 76 * created by Minor::Execute. 77 */ 78class MinorCPU : public BaseCPU 79{ 80 protected: | 1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 * This pipeline is carried in the MinorCPU::pipeline object. 74 * The exec_context interface is not carried by MinorCPU but by 75 * Minor::ExecContext objects 76 * created by Minor::Execute. 77 */ 78class MinorCPU : public BaseCPU 79{ 80 protected: |
81 /** Event for delayed wakeup of a thread */ 82 class ThreadActivateEvent : public Event 83 { 84 public: 85 MinorCPU &cpu; 86 ThreadID thread_id; 87 88 ThreadActivateEvent(MinorCPU &cpu_, ThreadID thread_id_) : 89 cpu(cpu_), thread_id(thread_id_) 90 { } 91 92 void process(); 93 }; 94 95 /** Events to wakeup each thread */ 96 std::vector<ThreadActivateEvent *> threadActivateEvents; 97 | |
98 /** pipeline is a container for the clockable pipeline stage objects. 99 * Elements of pipeline call TheISA to implement the model. */ 100 Minor::Pipeline *pipeline; 101 102 public: 103 /** Activity recording for pipeline. This belongs to Pipeline but 104 * stages will access it through the CPU as the MinorCPU object 105 * actually mediates idling behaviour */ --- 73 unchanged lines hidden (view full) --- 179 void signalDrainDone(); 180 void memWriteback(); 181 182 /** Switching interface from BaseCPU */ 183 void switchOut(); 184 void takeOverFrom(BaseCPU *old_cpu); 185 186 /** Thread activation interface from BaseCPU. */ | 81 /** pipeline is a container for the clockable pipeline stage objects. 82 * Elements of pipeline call TheISA to implement the model. */ 83 Minor::Pipeline *pipeline; 84 85 public: 86 /** Activity recording for pipeline. This belongs to Pipeline but 87 * stages will access it through the CPU as the MinorCPU object 88 * actually mediates idling behaviour */ --- 73 unchanged lines hidden (view full) --- 162 void signalDrainDone(); 163 void memWriteback(); 164 165 /** Switching interface from BaseCPU */ 166 void switchOut(); 167 void takeOverFrom(BaseCPU *old_cpu); 168 169 /** Thread activation interface from BaseCPU. */ |
187 void activateContext(ThreadID thread_id, Cycles delay); | 170 void activateContext(ThreadID thread_id); |
188 void suspendContext(ThreadID thread_id); 189 190 /** Interface for stages to signal that they have become active after 191 * a callback or eventq event where the pipeline itself may have 192 * already been idled. The stage argument should be from the 193 * enumeration Pipeline::StageId */ 194 void wakeupOnEvent(unsigned int stage_id); 195}; 196 197#endif /* __CPU_MINOR_CPU_HH__ */ | 171 void suspendContext(ThreadID thread_id); 172 173 /** Interface for stages to signal that they have become active after 174 * a callback or eventq event where the pipeline itself may have 175 * already been idled. The stage argument should be from the 176 * enumeration Pipeline::StageId */ 177 void wakeupOnEvent(unsigned int stage_id); 178}; 179 180#endif /* __CPU_MINOR_CPU_HH__ */ |