cpu.hh (11169:44b5c183c3cd) | cpu.hh (11331:cd5c48db28e6) |
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1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 93 unchanged lines hidden (view full) --- 102 /** The enclosing cpu */ 103 MinorCPU &cpu; 104 105 public: 106 MinorCPUPort(const std::string& name_, MinorCPU &cpu_) 107 : MasterPort(name_, &cpu_), cpu(cpu_) 108 { } 109 | 1/* 2 * Copyright (c) 2012-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 93 unchanged lines hidden (view full) --- 102 /** The enclosing cpu */ 103 MinorCPU &cpu; 104 105 public: 106 MinorCPUPort(const std::string& name_, MinorCPU &cpu_) 107 : MasterPort(name_, &cpu_), cpu(cpu_) 108 { } 109 |
110 protected: 111 /** Snooping a coherence request, do nothing. */ 112 virtual void recvTimingSnoopReq(PacketPtr pkt) { } | |
113 }; 114 115 protected: 116 /** Return a reference to the data port. */ 117 MasterPort &getDataPort() override; 118 119 /** Return a reference to the instruction port. */ 120 MasterPort &getInstPort() override; --- 55 unchanged lines hidden --- | 110 }; 111 112 protected: 113 /** Return a reference to the data port. */ 114 MasterPort &getDataPort() override; 115 116 /** Return a reference to the instruction port. */ 117 MasterPort &getInstPort() override; --- 55 unchanged lines hidden --- |