| MinorCPU.py (12563:8d59ed22ae79) | MinorCPU.py (13172:b816da4c5e9f) |
|---|---|
| 1# Copyright (c) 2012-2014 ARM Limited | 1# Copyright (c) 2012-2014,2018 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 135 unchanged lines hidden (view full) --- 145class MinorDefaultFloatSimdFU(MinorFU): 146 opClasses = minorMakeOpClassSet([ 147 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 148 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 149 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 150 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 151 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 152 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 135 unchanged lines hidden (view full) --- 145class MinorDefaultFloatSimdFU(MinorFU): 146 opClasses = minorMakeOpClassSet([ 147 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 148 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', 149 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 150 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 151 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 152 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', |
| 153 'SimdFloatMultAcc', 'SimdFloatSqrt']) | 153 'SimdFloatMultAcc', 'SimdFloatSqrt', 'SimdAes', 'SimdAesMix', 154 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash', 155 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3']) |
| 154 timings = [MinorFUTiming(description='FloatSimd', 155 srcRegsRelativeLats=[2])] 156 opLat = 6 157 158class MinorDefaultMemFU(MinorFU): 159 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 160 'FloatMemWrite']) 161 timings = [MinorFUTiming(description='Mem', --- 120 unchanged lines hidden --- | 156 timings = [MinorFUTiming(description='FloatSimd', 157 srcRegsRelativeLats=[2])] 158 opLat = 6 159 160class MinorDefaultMemFU(MinorFU): 161 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 162 'FloatMemWrite']) 163 timings = [MinorFUTiming(description='Mem', --- 120 unchanged lines hidden --- |