| MinorCPU.py (11567:560d7fbbddd1) | MinorCPU.py (11683:f1e198a028be) |
|---|---|
| 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138class MinorDefaultIntDivFU(MinorFU): 139 opClasses = minorMakeOpClassSet(['IntDiv']) 140 issueLat = 9 141 opLat = 9 142 143class MinorDefaultFloatSimdFU(MinorFU): 144 opClasses = minorMakeOpClassSet([ | 1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138class MinorDefaultIntDivFU(MinorFU): 139 opClasses = minorMakeOpClassSet(['IntDiv']) 140 issueLat = 9 141 opLat = 9 142 143class MinorDefaultFloatSimdFU(MinorFU): 144 opClasses = minorMakeOpClassSet([ |
| 145 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 146 'FloatSqrt', | 145 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult', 146 'FloatMultAcc', 'FloatDiv', 'FloatSqrt', |
| 147 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 148 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 149 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 150 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 151 'SimdFloatMultAcc', 'SimdFloatSqrt']) 152 timings = [MinorFUTiming(description='FloatSimd', 153 srcRegsRelativeLats=[2])] 154 opLat = 6 155 156class MinorDefaultMemFU(MinorFU): | 147 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt', 148 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc', 149 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp', 150 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult', 151 'SimdFloatMultAcc', 'SimdFloatSqrt']) 152 timings = [MinorFUTiming(description='FloatSimd', 153 srcRegsRelativeLats=[2])] 154 opLat = 6 155 156class MinorDefaultMemFU(MinorFU): |
| 157 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite']) | 157 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead', 158 'FloatMemWrite']) |
| 158 timings = [MinorFUTiming(description='Mem', 159 srcRegsRelativeLats=[1], extraAssumedLat=2)] 160 opLat = 1 161 162class MinorDefaultMiscFU(MinorFU): 163 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 164 opLat = 1 165 --- 113 unchanged lines hidden --- | 159 timings = [MinorFUTiming(description='Mem', 160 srcRegsRelativeLats=[1], extraAssumedLat=2)] 161 opLat = 1 162 163class MinorDefaultMiscFU(MinorFU): 164 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch']) 165 opLat = 1 166 --- 113 unchanged lines hidden --- |