1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 32 unchanged lines hidden (view full) --- 41# Andrew Bardsley 42 43from m5.defines import buildEnv 44from m5.params import * 45from m5.proxy import * 46from m5.SimObject import SimObject 47from BaseCPU import BaseCPU 48from DummyChecker import DummyChecker |
49from BranchPredictor import * |
50from TimingExpr import TimingExpr 51 52from FuncUnit import OpClass 53 54class MinorOpClass(SimObject): 55 """Boxing of OpClass to get around build problems and provide a hook for 56 future additions to OpClass checks""" 57 --- 203 unchanged lines hidden (view full) --- 261 262 executeAllowEarlyMemoryIssue = Param.Bool(True, 263 "Allow mem refs to be issued to the LSQ before reaching the head of" 264 " the in flight insts queue") 265 266 enableIdling = Param.Bool(True, 267 "Enable cycle skipping when the processor is idle\n"); 268 |
269 branchPred = Param.BranchPredictor(TournamentBP( |
270 numThreads = Parent.numThreads), "Branch Predictor") 271 272 def addCheckerCpu(self): 273 print "Checker not yet supported by MinorCPU" 274 exit(1) |