1# Copyright (c) 2012-2014 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Gabe Black
40# Nathan Binkert
41# Andrew Bardsley
42
43from m5.defines import buildEnv
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47from BaseCPU import BaseCPU
48from DummyChecker import DummyChecker
49from BranchPredictor import *
50from TimingExpr import TimingExpr
51
52from FuncUnit import OpClass
53
54class MinorOpClass(SimObject):
55 """Boxing of OpClass to get around build problems and provide a hook for
56 future additions to OpClass checks"""
57
58 type = 'MinorOpClass'
59 cxx_header = "cpu/minor/func_unit.hh"
60
61 opClass = Param.OpClass("op class to match")
62
63class MinorOpClassSet(SimObject):
64 """A set of matchable op classes"""
65
66 type = 'MinorOpClassSet'
67 cxx_header = "cpu/minor/func_unit.hh"
68
69 opClasses = VectorParam.MinorOpClass([], "op classes to be matched."
70 " An empty list means any class")
71
72class MinorFUTiming(SimObject):
73 type = 'MinorFUTiming'
74 cxx_header = "cpu/minor/func_unit.hh"
75
76 mask = Param.UInt64(0, "mask for testing ExtMachInst")
77 match = Param.UInt64(0, "match value for testing ExtMachInst:"
78 " (ext_mach_inst & mask) == match")
79 suppress = Param.Bool(False, "if true, this inst. is not executed by"
80 " this FU")
81 extraCommitLat = Param.Cycles(0, "extra cycles to stall commit for"
82 " this inst.")
83 extraCommitLatExpr = Param.TimingExpr(NULL, "extra cycles as a"
84 " run-time evaluated expression")
85 extraAssumedLat = Param.Cycles(0, "extra cycles to add to scoreboard"
86 " retire time for this insts dest registers once it leaves the"
87 " functional unit. For mem refs, if this is 0, the result's time"
88 " is marked as unpredictable and no forwarding can take place.")
89 srcRegsRelativeLats = VectorParam.Cycles("the maximum number of cycles"
90 " after inst. issue that each src reg can be available for this"
91 " inst. to issue")
92 opClasses = Param.MinorOpClassSet(MinorOpClassSet(),
93 "op classes to be considered for this decode. An empty set means any"
94 " class")
95 description = Param.String('', "description string of the decoding/inst."
96 " class")
97
98def minorMakeOpClassSet(op_classes):
99 """Make a MinorOpClassSet from a list of OpClass enum value strings"""
100 def boxOpClass(op_class):
101 return MinorOpClass(opClass=op_class)
102
103 return MinorOpClassSet(opClasses=map(boxOpClass, op_classes))
104
105class MinorFU(SimObject):
106 type = 'MinorFU'
107 cxx_header = "cpu/minor/func_unit.hh"
108
109 opClasses = Param.MinorOpClassSet(MinorOpClassSet(), "type of operations"
110 " allowed on this functional unit")
111 opLat = Param.Cycles(1, "latency in cycles")
112 issueLat = Param.Cycles(1, "cycles until another instruction can be"
113 " issued")
114 timings = VectorParam.MinorFUTiming([], "extra decoding rules")
115
116 cantForwardFromFUIndices = VectorParam.Unsigned([],
117 "list of FU indices from which this FU can't receive and early"
118 " (forwarded) result")
119
120class MinorFUPool(SimObject):
121 type = 'MinorFUPool'
122 cxx_header = "cpu/minor/func_unit.hh"
123
124 funcUnits = VectorParam.MinorFU("functional units")
125
126class MinorDefaultIntFU(MinorFU):
127 opClasses = minorMakeOpClassSet(['IntAlu'])
128 timings = [MinorFUTiming(description="Int",
129 srcRegsRelativeLats=[2])]
130 opLat = 3
131
132class MinorDefaultIntMulFU(MinorFU):
133 opClasses = minorMakeOpClassSet(['IntMult'])
134 timings = [MinorFUTiming(description='Mul',
135 srcRegsRelativeLats=[0])]
136 opLat = 3
137
138class MinorDefaultIntDivFU(MinorFU):
139 opClasses = minorMakeOpClassSet(['IntDiv'])
140 issueLat = 9
141 opLat = 9
142
143class MinorDefaultFloatSimdFU(MinorFU):
144 opClasses = minorMakeOpClassSet([
145 'FloatAdd', 'FloatCmp', 'FloatCvt', 'FloatMisc', 'FloatMult',
146 'FloatMultAcc', 'FloatDiv', 'FloatSqrt',
147 'SimdAdd', 'SimdAddAcc', 'SimdAlu', 'SimdCmp', 'SimdCvt',
148 'SimdMisc', 'SimdMult', 'SimdMultAcc', 'SimdShift', 'SimdShiftAcc',
149 'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
150 'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
151 'SimdFloatMultAcc', 'SimdFloatSqrt'])
152 timings = [MinorFUTiming(description='FloatSimd',
153 srcRegsRelativeLats=[2])]
154 opLat = 6
155
156class MinorDefaultMemFU(MinorFU):
157 opClasses = minorMakeOpClassSet(['MemRead', 'MemWrite', 'FloatMemRead',
158 'FloatMemWrite'])
159 timings = [MinorFUTiming(description='Mem',
160 srcRegsRelativeLats=[1], extraAssumedLat=2)]
161 opLat = 1
162
163class MinorDefaultMiscFU(MinorFU):
164 opClasses = minorMakeOpClassSet(['IprAccess', 'InstPrefetch'])
165 opLat = 1
166
167class MinorDefaultFUPool(MinorFUPool):
168 funcUnits = [MinorDefaultIntFU(), MinorDefaultIntFU(),
169 MinorDefaultIntMulFU(), MinorDefaultIntDivFU(),
170 MinorDefaultFloatSimdFU(), MinorDefaultMemFU(),
171 MinorDefaultMiscFU()]
172
173class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
174
175class MinorCPU(BaseCPU):
176 type = 'MinorCPU'
177 cxx_header = "cpu/minor/cpu.hh"
178
179 @classmethod
180 def memory_mode(cls):
181 return 'timing'
182
183 @classmethod
184 def require_caches(cls):
185 return True
186
187 @classmethod
188 def support_take_over(cls):
189 return True
190
191 threadPolicy = Param.ThreadPolicy('RoundRobin',
192 "Thread scheduling policy")
193 fetch1FetchLimit = Param.Unsigned(1,
194 "Number of line fetches allowable in flight at once")
195 fetch1LineSnapWidth = Param.Unsigned(0,
196 "Fetch1 'line' fetch snap size in bytes"
197 " (0 means use system cache line size)")
198 fetch1LineWidth = Param.Unsigned(0,
199 "Fetch1 maximum fetch size in bytes (0 means use system cache"
200 " line size)")
201 fetch1ToFetch2ForwardDelay = Param.Cycles(1,
202 "Forward cycle delay from Fetch1 to Fetch2 (1 means next cycle)")
203 fetch1ToFetch2BackwardDelay = Param.Cycles(1,
204 "Backward cycle delay from Fetch2 to Fetch1 for branch prediction"
205 " signalling (0 means in the same cycle, 1 mean the next cycle)")
206
207 fetch2InputBufferSize = Param.Unsigned(2,
208 "Size of input buffer to Fetch2 in cycles-worth of insts.")
209 fetch2ToDecodeForwardDelay = Param.Cycles(1,
210 "Forward cycle delay from Fetch2 to Decode (1 means next cycle)")
211 fetch2CycleInput = Param.Bool(True,
212 "Allow Fetch2 to cross input lines to generate full output each"
213 " cycle")
214
215 decodeInputBufferSize = Param.Unsigned(3,
216 "Size of input buffer to Decode in cycles-worth of insts.")
217 decodeToExecuteForwardDelay = Param.Cycles(1,
218 "Forward cycle delay from Decode to Execute (1 means next cycle)")
219 decodeInputWidth = Param.Unsigned(2,
220 "Width (in instructions) of input to Decode (and implicitly"
221 " Decode's own width)")
222 decodeCycleInput = Param.Bool(True,
223 "Allow Decode to pack instructions from more than one input cycle"
224 " to fill its output each cycle")
225
226 executeInputWidth = Param.Unsigned(2,
227 "Width (in instructions) of input to Execute")
228 executeCycleInput = Param.Bool(True,
229 "Allow Execute to use instructions from more than one input cycle"
230 " each cycle")
231 executeIssueLimit = Param.Unsigned(2,
232 "Number of issuable instructions in Execute each cycle")
233 executeMemoryIssueLimit = Param.Unsigned(1,
234 "Number of issuable memory instructions in Execute each cycle")
235 executeCommitLimit = Param.Unsigned(2,
236 "Number of committable instructions in Execute each cycle")
237 executeMemoryCommitLimit = Param.Unsigned(1,
238 "Number of committable memory references in Execute each cycle")
239 executeInputBufferSize = Param.Unsigned(7,
240 "Size of input buffer to Execute in cycles-worth of insts.")
241 executeMemoryWidth = Param.Unsigned(0,
242 "Width (and snap) in bytes of the data memory interface. (0 mean use"
243 " the system cacheLineSize)")
244 executeMaxAccessesInMemory = Param.Unsigned(2,
245 "Maximum number of concurrent accesses allowed to the memory system"
246 " from the dcache port")
247 executeLSQMaxStoreBufferStoresPerCycle = Param.Unsigned(2,
248 "Maximum number of stores that the store buffer can issue per cycle")
249 executeLSQRequestsQueueSize = Param.Unsigned(1,
250 "Size of LSQ requests queue (address translation queue)")
251 executeLSQTransfersQueueSize = Param.Unsigned(2,
252 "Size of LSQ transfers queue (memory transaction queue)")
253 executeLSQStoreBufferSize = Param.Unsigned(5,
254 "Size of LSQ store buffer")
255 executeBranchDelay = Param.Cycles(1,
256 "Delay from Execute deciding to branch and Fetch1 reacting"
257 " (1 means next cycle)")
258
259 executeFuncUnits = Param.MinorFUPool(MinorDefaultFUPool(),
260 "FUlines for this processor")
261
262 executeSetTraceTimeOnCommit = Param.Bool(True,
263 "Set inst. trace times to be commit times")
264 executeSetTraceTimeOnIssue = Param.Bool(False,
265 "Set inst. trace times to be issue times")
266
267 executeAllowEarlyMemoryIssue = Param.Bool(True,
268 "Allow mem refs to be issued to the LSQ before reaching the head of"
269 " the in flight insts queue")
270
271 enableIdling = Param.Bool(True,
272 "Enable cycle skipping when the processor is idle\n");
273
274 branchPred = Param.BranchPredictor(TournamentBP(
275 numThreads = Parent.numThreads), "Branch Predictor")
276
277 def addCheckerCpu(self):
278 print "Checker not yet supported by MinorCPU"
279 exit(1)