base.hh (11168:f98eb2da15a4) base.hh (11341:bda2c39fd9fd)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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75 * depending on the specifics of the underlying hardware/drivers.
76 */
77class BaseKvmCPU : public BaseCPU
78{
79 public:
80 BaseKvmCPU(BaseKvmCPUParams *params);
81 virtual ~BaseKvmCPU();
82
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 66 unchanged lines hidden (view full) ---

75 * depending on the specifics of the underlying hardware/drivers.
76 */
77class BaseKvmCPU : public BaseCPU
78{
79 public:
80 BaseKvmCPU(BaseKvmCPUParams *params);
81 virtual ~BaseKvmCPU();
82
83 void init();
84 void startup();
85 void regStats();
83 void init() override;
84 void startup() override;
85 void regStats() override;
86
87 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
88 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
89
90 DrainState drain() override;
91 void drainResume() override;
92
86
87 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
88 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
89
90 DrainState drain() override;
91 void drainResume() override;
92
93 void switchOut();
94 void takeOverFrom(BaseCPU *cpu);
93 void switchOut() override;
94 void takeOverFrom(BaseCPU *cpu) override;
95
95
96 void verifyMemoryMode() const;
96 void verifyMemoryMode() const override;
97
97
98 MasterPort &getDataPort() { return dataPort; }
99 MasterPort &getInstPort() { return instPort; }
98 MasterPort &getDataPort() override { return dataPort; }
99 MasterPort &getInstPort() override { return instPort; }
100
101 void wakeup(ThreadID tid = 0) override;
100
101 void wakeup(ThreadID tid = 0) override;
102 void activateContext(ThreadID thread_num);
103 void suspendContext(ThreadID thread_num);
102 void activateContext(ThreadID thread_num) override;
103 void suspendContext(ThreadID thread_num) override;
104 void deallocateContext(ThreadID thread_num);
104 void deallocateContext(ThreadID thread_num);
105 void haltContext(ThreadID thread_num);
105 void haltContext(ThreadID thread_num) override;
106
106
107 ThreadContext *getContext(int tn);
107 ThreadContext *getContext(int tn) override;
108
108
109 Counter totalInsts() const;
110 Counter totalOps() const;
109 Counter totalInsts() const override;
110 Counter totalOps() const override;
111
112 /** Dump the internal state to the terminal. */
113 virtual void dump() const;
114
115 /**
116 * Force an exit from KVM.
117 *
118 * Send a signal to the thread owning this vCPU to get it to exit

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112 /** Dump the internal state to the terminal. */
113 virtual void dump() const;
114
115 /**
116 * Force an exit from KVM.
117 *
118 * Send a signal to the thread owning this vCPU to get it to exit

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