96,97c96,97
< CpuPort &getDataPort() { return dataPort; }
< CpuPort &getInstPort() { return instPort; }
---
> MasterPort &getDataPort() { return dataPort; }
> MasterPort &getInstPort() { return instPort; }
405a406,432
>
> /**
> * KVM memory port. Uses the default MasterPort behavior, but
> * panics on timing accesses.
> */
> class KVMCpuPort : public MasterPort
> {
>
> public:
> KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu)
> : MasterPort(_name, _cpu)
> { }
>
> protected:
> bool recvTimingResp(PacketPtr pkt)
> {
> panic("The KVM CPU doesn't expect recvTimingResp!\n");
> return true;
> }
>
> void recvRetry()
> {
> panic("The KVM CPU doesn't expect recvRetry!\n");
> }
>
> };
>
407c434
< CpuPort dataPort;
---
> KVMCpuPort dataPort;
410c437
< CpuPort instPort;
---
> KVMCpuPort instPort;