base.hh (9684:00dca8a9b560) | base.hh (9688:cce7dd32aed3) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 79 unchanged lines hidden (view full) --- 88 unsigned int drain(DrainManager *dm); 89 void drainResume(); 90 91 void switchOut(); 92 void takeOverFrom(BaseCPU *cpu); 93 94 void verifyMemoryMode() const; 95 | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 79 unchanged lines hidden (view full) --- 88 unsigned int drain(DrainManager *dm); 89 void drainResume(); 90 91 void switchOut(); 92 void takeOverFrom(BaseCPU *cpu); 93 94 void verifyMemoryMode() const; 95 |
96 CpuPort &getDataPort() { return dataPort; } 97 CpuPort &getInstPort() { return instPort; } | 96 MasterPort &getDataPort() { return dataPort; } 97 MasterPort &getInstPort() { return instPort; } |
98 99 void wakeup(); 100 void activateContext(ThreadID thread_num, Cycles delay); 101 void suspendContext(ThreadID thread_num); 102 void deallocateContext(ThreadID thread_num); 103 void haltContext(ThreadID thread_num); 104 105 ThreadContext *getContext(int tn); --- 292 unchanged lines hidden (view full) --- 398 int ioctl(int request, void *p1) const { 399 return ioctl(request, (long)p1); 400 } 401 int ioctl(int request) const { 402 return ioctl(request, 0L); 403 } 404 /** @} */ 405 | 98 99 void wakeup(); 100 void activateContext(ThreadID thread_num, Cycles delay); 101 void suspendContext(ThreadID thread_num); 102 void deallocateContext(ThreadID thread_num); 103 void haltContext(ThreadID thread_num); 104 105 ThreadContext *getContext(int tn); --- 292 unchanged lines hidden (view full) --- 398 int ioctl(int request, void *p1) const { 399 return ioctl(request, (long)p1); 400 } 401 int ioctl(int request) const { 402 return ioctl(request, 0L); 403 } 404 /** @} */ 405 |
406 407 /** 408 * KVM memory port. Uses the default MasterPort behavior, but 409 * panics on timing accesses. 410 */ 411 class KVMCpuPort : public MasterPort 412 { 413 414 public: 415 KVMCpuPort(const std::string &_name, BaseKvmCPU *_cpu) 416 : MasterPort(_name, _cpu) 417 { } 418 419 protected: 420 bool recvTimingResp(PacketPtr pkt) 421 { 422 panic("The KVM CPU doesn't expect recvTimingResp!\n"); 423 return true; 424 } 425 426 void recvRetry() 427 { 428 panic("The KVM CPU doesn't expect recvRetry!\n"); 429 } 430 431 }; 432 |
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406 /** Port for data requests */ | 433 /** Port for data requests */ |
407 CpuPort dataPort; | 434 KVMCpuPort dataPort; |
408 409 /** Unused dummy port for the instruction interface */ | 435 436 /** Unused dummy port for the instruction interface */ |
410 CpuPort instPort; | 437 KVMCpuPort instPort; |
411 412 /** Pre-allocated MMIO memory request */ 413 Request mmio_req; 414 415 /** 416 * Is the gem5 context dirty? Set to true to force an update of 417 * the KVM vCPU state upon the next call to kvmRun(). 418 */ --- 106 unchanged lines hidden --- | 438 439 /** Pre-allocated MMIO memory request */ 440 Request mmio_req; 441 442 /** 443 * Is the gem5 context dirty? Set to true to force an update of 444 * the KVM vCPU state upon the next call to kvmRun(). 445 */ --- 106 unchanged lines hidden --- |