1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ron Dreslinski 30 */ 31 32#include <string> 33#include <vector> 34 35#include "cpu/base.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/intr_control.hh" 38#include "sim/builder.hh" 39#include "sim/sim_object.hh" 40 41using namespace std; 42
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43IntrControl::IntrControl(const string &name, BaseCPU *c)
44 : SimObject(name), cpu(c)
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43IntrControl::IntrControl(const string &name, System *s) 44 : SimObject(name), sys(s) |
45{} 46
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47/* @todo
48 *Fix the cpu sim object parameter to be a system pointer
49 *instead, to avoid some extra dereferencing
50 */
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47void 48IntrControl::post(int int_num, int index) 49{
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54 std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
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50 std::vector<ThreadContext *> &tcvec = sys->threadContexts; |
51 BaseCPU *temp = tcvec[0]->getCpuPtr(); 52 temp->post_interrupt(int_num, index); 53} 54 55void 56IntrControl::post(int cpu_id, int int_num, int index) 57{
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62 std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
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58 std::vector<ThreadContext *> &tcvec = sys->threadContexts; |
59 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 60 temp->post_interrupt(int_num, index); 61} 62 63void 64IntrControl::clear(int int_num, int index) 65{
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70 std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
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66 std::vector<ThreadContext *> &tcvec = sys->threadContexts; |
67 BaseCPU *temp = tcvec[0]->getCpuPtr(); 68 temp->clear_interrupt(int_num, index); 69} 70 71void 72IntrControl::clear(int cpu_id, int int_num, int index) 73{
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78 std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
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74 std::vector<ThreadContext *> &tcvec = sys->threadContexts; |
75 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 76 temp->clear_interrupt(int_num, index); 77} 78 79BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 80
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85 SimObjectParam<BaseCPU *> cpu;
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81 SimObjectParam<System *> sys; |
82 83END_DECLARE_SIM_OBJECT_PARAMS(IntrControl) 84 85BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl) 86
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91 INIT_PARAM(cpu, "the cpu")
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87 INIT_PARAM(sys, "the system we are part of") |
88 89END_INIT_SIM_OBJECT_PARAMS(IntrControl) 90 91CREATE_SIM_OBJECT(IntrControl) 92{
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97 return new IntrControl(getInstanceName(), cpu);
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93 return new IntrControl(getInstanceName(), sys); |
94} 95 96REGISTER_SIM_OBJECT("IntrControl", IntrControl)
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