1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#include <string> 33#include <vector> 34 35#include "cpu/base.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/intr_control.hh" |
38#include "sim/sim_object.hh" 39 40using namespace std; 41 |
42IntrControl::IntrControl(const Params *p) 43 : SimObject(p), sys(p->sys) |
44{} 45 46void 47IntrControl::post(int int_num, int index) 48{ 49 std::vector<ThreadContext *> &tcvec = sys->threadContexts; 50 BaseCPU *temp = tcvec[0]->getCpuPtr(); 51 temp->post_interrupt(int_num, index); --- 21 unchanged lines hidden (view full) --- 73 std::vector<ThreadContext *> &tcvec = sys->threadContexts; 74 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 75 temp->clear_interrupt(int_num, index); 76} 77 78IntrControl * 79IntrControlParams::create() 80{ |
81 return new IntrControl(this); |
82} |