1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#include <string> 33#include <vector> 34 35#include "cpu/base.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/intr_control.hh" |
38#include "params/IntrControl.hh" |
39#include "sim/sim_object.hh" 40 41using namespace std; 42 43IntrControl::IntrControl(const string &name, System *s) 44 : SimObject(name), sys(s) 45{} 46 --- 24 unchanged lines hidden (view full) --- 71void 72IntrControl::clear(int cpu_id, int int_num, int index) 73{ 74 std::vector<ThreadContext *> &tcvec = sys->threadContexts; 75 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr(); 76 temp->clear_interrupt(int_num, index); 77} 78 |
79IntrControl * 80IntrControlParams::create() |
81{ |
82 return new IntrControl(name, sys); |
83} |