1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ron Dreslinski
30 */
31
32#include <string>
33#include <vector>
34
35#include "cpu/base.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/intr_control.hh"
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ron Dreslinski
30 */
31
32#include <string>
33#include <vector>
34
35#include "cpu/base.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/intr_control.hh"
|
38#include "params/IntrControl.hh"
| |
39#include "sim/sim_object.hh"
40
41using namespace std;
42
| 38#include "sim/sim_object.hh"
39
40using namespace std;
41
|
43IntrControl::IntrControl(const string &name, System *s)
44 : SimObject(name), sys(s)
| 42IntrControl::IntrControl(const Params *p)
43 : SimObject(p), sys(p->sys)
|
45{}
46
47void
48IntrControl::post(int int_num, int index)
49{
50 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
51 BaseCPU *temp = tcvec[0]->getCpuPtr();
52 temp->post_interrupt(int_num, index);
53}
54
55void
56IntrControl::post(int cpu_id, int int_num, int index)
57{
58 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
59 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
60 temp->post_interrupt(int_num, index);
61}
62
63void
64IntrControl::clear(int int_num, int index)
65{
66 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
67 BaseCPU *temp = tcvec[0]->getCpuPtr();
68 temp->clear_interrupt(int_num, index);
69}
70
71void
72IntrControl::clear(int cpu_id, int int_num, int index)
73{
74 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
75 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
76 temp->clear_interrupt(int_num, index);
77}
78
79IntrControl *
80IntrControlParams::create()
81{
| 44{}
45
46void
47IntrControl::post(int int_num, int index)
48{
49 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
50 BaseCPU *temp = tcvec[0]->getCpuPtr();
51 temp->post_interrupt(int_num, index);
52}
53
54void
55IntrControl::post(int cpu_id, int int_num, int index)
56{
57 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
58 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
59 temp->post_interrupt(int_num, index);
60}
61
62void
63IntrControl::clear(int int_num, int index)
64{
65 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
66 BaseCPU *temp = tcvec[0]->getCpuPtr();
67 temp->clear_interrupt(int_num, index);
68}
69
70void
71IntrControl::clear(int cpu_id, int int_num, int index)
72{
73 std::vector<ThreadContext *> &tcvec = sys->threadContexts;
74 BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
75 temp->clear_interrupt(int_num, index);
76}
77
78IntrControl *
79IntrControlParams::create()
80{
|
82 return new IntrControl(name, sys);
| 81 return new IntrControl(this);
|
83}
| 82}
|