1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 21 unchanged lines hidden (view full) --- 30 */ 31 32#ifndef __CPU_INTELTRACE_HH__ 33#define __CPU_INTELTRACE_HH__ 34 35#include "base/trace.hh" 36#include "base/types.hh" 37#include "cpu/static_inst.hh" |
38#include "cpu/thread_context.hh" |
39#include "debug/ExecEnable.hh" 40#include "debug/ExecSpeculative.hh" 41#include "params/IntelTrace.hh" 42#include "sim/insttracer.hh" 43 |
44namespace Trace { 45 46class IntelTraceRecord : public InstRecord 47{ 48 public: 49 IntelTraceRecord(Tick _when, ThreadContext *_thread, 50 const StaticInstPtr _staticInst, TheISA::PCState _pc, 51 bool spec, const StaticInstPtr _macroStaticInst = NULL) --- 37 unchanged lines hidden --- |