1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __CPU_INST_PB_TRACE_HH__
41#define __CPU_INST_PB_TRACE_HH__
42
43#include "arch/types.hh"
44#include "base/trace.hh"
45#include "base/types.hh"
46#include "cpu/static_inst_fwd.hh"
47#include "params/InstPBTrace.hh"
48#include "proto/protoio.hh"
49#include "sim/insttracer.hh"
50
51class ThreadContext;
52
53namespace ProtoMessage {
54class Inst;
55}
56
57namespace Trace {
58
59/**
60 * This in an instruction tracer that records the flow of instructions through
61 * multiple cpus and systems to a protobuf file specified by proto/inst.proto
62 * for further analysis.
63 */
64
65class InstPBTraceRecord : public InstRecord
66{
67 public:
68 InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc,
69 const StaticInstPtr si, TheISA::PCState pc,
70 const StaticInstPtr mi = NULL)
71 : InstRecord(when, tc, si, pc, mi), tracer(_tracer)
72 {}
73
74 /** called by the cpu when the instruction commits.
75 * This implementation of dump calls InstPBTrace to output the contents to a
76 * protobuf file
77 */
| 1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Ali Saidi
38 */
39
40#ifndef __CPU_INST_PB_TRACE_HH__
41#define __CPU_INST_PB_TRACE_HH__
42
43#include "arch/types.hh"
44#include "base/trace.hh"
45#include "base/types.hh"
46#include "cpu/static_inst_fwd.hh"
47#include "params/InstPBTrace.hh"
48#include "proto/protoio.hh"
49#include "sim/insttracer.hh"
50
51class ThreadContext;
52
53namespace ProtoMessage {
54class Inst;
55}
56
57namespace Trace {
58
59/**
60 * This in an instruction tracer that records the flow of instructions through
61 * multiple cpus and systems to a protobuf file specified by proto/inst.proto
62 * for further analysis.
63 */
64
65class InstPBTraceRecord : public InstRecord
66{
67 public:
68 InstPBTraceRecord(InstPBTrace& _tracer, Tick when, ThreadContext *tc,
69 const StaticInstPtr si, TheISA::PCState pc,
70 const StaticInstPtr mi = NULL)
71 : InstRecord(when, tc, si, pc, mi), tracer(_tracer)
72 {}
73
74 /** called by the cpu when the instruction commits.
75 * This implementation of dump calls InstPBTrace to output the contents to a
76 * protobuf file
77 */
|
79
80 protected:
81 InstPBTrace& tracer;
82
83};
84
85class InstPBTrace : public InstTracer
86{
87 public:
88 InstPBTrace(const InstPBTraceParams *p);
89 virtual ~InstPBTrace();
90
91 InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
92 StaticInstPtr si, TheISA::PCState pc, const
| 79
80 protected:
81 InstPBTrace& tracer;
82
83};
84
85class InstPBTrace : public InstTracer
86{
87 public:
88 InstPBTrace(const InstPBTraceParams *p);
89 virtual ~InstPBTrace();
90
91 InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
92 StaticInstPtr si, TheISA::PCState pc, const
|
94
95 protected:
96 /** One output stream for the entire simulation.
97 * We encode the CPU & system ID so all we need is a single file
98 */
99 static ProtoOutputStream *traceStream;
100
101
102 /** This is the message were working on writing. The majority of the message
103 * exists however the memory accesses will be delayed.
104 */
105 ProtoMessage::Inst *curMsg;
106
107 /** Create the output file and write the header into it
108 * @param filename the file to create (if ends with .gz it will be
109 * compressed)
110 */
111 void createTraceFile(std::string filename);
112
113 /** If there is a pending message still write it out and then close the file
114 */
115 void closeStreams();
116
117 /** Write an instruction to the trace file
118 * @param tc thread context for the cpu ID
119 * @param si for the machInst and opClass
120 * @param pc for the PC Addr
121 */
122 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
123
124 /** Write a memory request to the trace file as part of the cur instruction
125 * @param si for the machInst and opClass
126 * @param a address of the request
127 * @param s size of the request
128 * @param f flags for the request
129 */
130 void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
131
132 friend class InstPBTraceRecord;
133};
134} // namespace Trace
135#endif // __CPU_INST_PB_TRACE_HH__
| 94
95 protected:
96 /** One output stream for the entire simulation.
97 * We encode the CPU & system ID so all we need is a single file
98 */
99 static ProtoOutputStream *traceStream;
100
101
102 /** This is the message were working on writing. The majority of the message
103 * exists however the memory accesses will be delayed.
104 */
105 ProtoMessage::Inst *curMsg;
106
107 /** Create the output file and write the header into it
108 * @param filename the file to create (if ends with .gz it will be
109 * compressed)
110 */
111 void createTraceFile(std::string filename);
112
113 /** If there is a pending message still write it out and then close the file
114 */
115 void closeStreams();
116
117 /** Write an instruction to the trace file
118 * @param tc thread context for the cpu ID
119 * @param si for the machInst and opClass
120 * @param pc for the PC Addr
121 */
122 void traceInst(ThreadContext *tc, StaticInstPtr si, TheISA::PCState pc);
123
124 /** Write a memory request to the trace file as part of the cur instruction
125 * @param si for the machInst and opClass
126 * @param a address of the request
127 * @param s size of the request
128 * @param f flags for the request
129 */
130 void traceMem(StaticInstPtr si, Addr a, Addr s, unsigned f);
131
132 friend class InstPBTraceRecord;
133};
134} // namespace Trace
135#endif // __CPU_INST_PB_TRACE_HH__
|