exetrace.hh (2670:9107b8bd08cd) exetrace.hh (2680:246e7104f744)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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33#define __EXETRACE_HH__
34
35#include <fstream>
36#include <vector>
37
38#include "sim/host.hh"
39#include "cpu/inst_seq.hh" // for InstSeqNum
40#include "base/trace.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 24 unchanged lines hidden (view full) ---

33#define __EXETRACE_HH__
34
35#include <fstream>
36#include <vector>
37
38#include "sim/host.hh"
39#include "cpu/inst_seq.hh" // for InstSeqNum
40#include "base/trace.hh"
41#include "cpu/exec_context.hh"
41#include "cpu/thread_context.hh"
42#include "cpu/static_inst.hh"
43
44class BaseCPU;
45
46
47namespace Trace {
48
49class InstRecord : public Record

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168 iregs = new iRegFile;
169
170 memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
171 regs_valid = true;
172}
173
174inline
175InstRecord *
42#include "cpu/static_inst.hh"
43
44class BaseCPU;
45
46
47namespace Trace {
48
49class InstRecord : public Record

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168 iregs = new iRegFile;
169
170 memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
171 regs_valid = true;
172}
173
174inline
175InstRecord *
176getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
176getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
177 const StaticInstPtr staticInst,
178 Addr pc, int thread = 0)
179{
180 if (DTRACE(InstExec) &&
177 const StaticInstPtr staticInst,
178 Addr pc, int thread = 0)
179{
180 if (DTRACE(InstExec) &&
181 (InstRecord::traceMisspec() || !xc->misspeculating())) {
181 (InstRecord::traceMisspec() || !tc->misspeculating())) {
182 return new InstRecord(cycle, cpu, staticInst, pc,
182 return new InstRecord(cycle, cpu, staticInst, pc,
183 xc->misspeculating(), thread);
183 tc->misspeculating(), thread);
184 }
185
186 return NULL;
187}
188
189
190}
191
192#endif // __EXETRACE_HH__
184 }
185
186 return NULL;
187}
188
189
190}
191
192#endif // __EXETRACE_HH__