1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __EXETRACE_HH__
33#define __EXETRACE_HH__
34
35#include <cstring>
36#include <fstream>
37#include <vector>
38
39#include "base/trace.hh"
40#include "cpu/inst_seq.hh" // for InstSeqNum
41#include "cpu/static_inst.hh"
42#include "cpu/thread_context.hh"
43#include "sim/host.hh"
44
45class ThreadContext;
46
47
48namespace Trace {
49
50class InstRecord
51{
52 protected:
53 typedef TheISA::IntRegFile IntRegFile;
54
55 Tick when;
56
57 // The following fields are initialized by the constructor and
58 // thus guaranteed to be valid.
59 ThreadContext *thread;
60 // need to make this ref-counted so it doesn't go away before we
61 // dump the record
62 StaticInstPtr staticInst;
63 Addr PC;
64 bool misspeculating;
65
66 // The remaining fields are only valid for particular instruction
67 // types (e.g, addresses for memory ops) or when particular
68 // options are enabled (e.g., tracing full register contents).
69 // Each data field has an associated valid flag to indicate
70 // whether the data field is valid.
71 Addr addr;
72 bool addr_valid;
73
74 union {
75 uint64_t as_int;
76 double as_double;
77 } data;
78 enum {
79 DataInvalid = 0,
80 DataInt8 = 1, // set to equal number of bytes
81 DataInt16 = 2,
82 DataInt32 = 4,
83 DataInt64 = 8,
84 DataDouble = 3
85 } data_status;
86
87 InstSeqNum fetch_seq;
88 bool fetch_seq_valid;
89
90 InstSeqNum cp_seq;
91 bool cp_seq_valid;
92
93 struct iRegFile {
94 IntRegFile regs;
95 };
96 iRegFile *iregs;
97 bool regs_valid;
98
99 public:
100 InstRecord(Tick _when, ThreadContext *_thread,
101 const StaticInstPtr &_staticInst,
102 Addr _pc, bool spec)
103 : when(_when), thread(_thread),
104 staticInst(_staticInst), PC(_pc),
105 misspeculating(spec)
106 {
107 data_status = DataInvalid;
108 addr_valid = false;
109 regs_valid = false;
110
111 fetch_seq_valid = false;
112 cp_seq_valid = false;
113 }
114
115 ~InstRecord() { }
116
117 void setAddr(Addr a) { addr = a; addr_valid = true; }
118
119 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
120 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
121 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
122 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
123
124 void setData(int64_t d) { setData((uint64_t)d); }
125 void setData(int32_t d) { setData((uint32_t)d); }
126 void setData(int16_t d) { setData((uint16_t)d); }
127 void setData(int8_t d) { setData((uint8_t)d); }
128
129 void setData(double d) { data.as_double = d; data_status = DataDouble; }
130
131 void setFetchSeq(InstSeqNum seq)
132 { fetch_seq = seq; fetch_seq_valid = true; }
133
134 void setCPSeq(InstSeqNum seq)
135 { cp_seq = seq; cp_seq_valid = true; }
136
137 void setRegs(const IntRegFile ®s);
138
139 void dump();
140};
141
142
143inline void
144InstRecord::setRegs(const IntRegFile ®s)
145{
146 if (!iregs)
147 iregs = new iRegFile;
148
149 std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
150 regs_valid = true;
151}
152
153inline InstRecord *
154getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
155 Addr pc)
156{
157 if (!IsOn(ExecEnable))
158 return NULL;
159
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __EXETRACE_HH__
33#define __EXETRACE_HH__
34
35#include <cstring>
36#include <fstream>
37#include <vector>
38
39#include "base/trace.hh"
40#include "cpu/inst_seq.hh" // for InstSeqNum
41#include "cpu/static_inst.hh"
42#include "cpu/thread_context.hh"
43#include "sim/host.hh"
44
45class ThreadContext;
46
47
48namespace Trace {
49
50class InstRecord
51{
52 protected:
53 typedef TheISA::IntRegFile IntRegFile;
54
55 Tick when;
56
57 // The following fields are initialized by the constructor and
58 // thus guaranteed to be valid.
59 ThreadContext *thread;
60 // need to make this ref-counted so it doesn't go away before we
61 // dump the record
62 StaticInstPtr staticInst;
63 Addr PC;
64 bool misspeculating;
65
66 // The remaining fields are only valid for particular instruction
67 // types (e.g, addresses for memory ops) or when particular
68 // options are enabled (e.g., tracing full register contents).
69 // Each data field has an associated valid flag to indicate
70 // whether the data field is valid.
71 Addr addr;
72 bool addr_valid;
73
74 union {
75 uint64_t as_int;
76 double as_double;
77 } data;
78 enum {
79 DataInvalid = 0,
80 DataInt8 = 1, // set to equal number of bytes
81 DataInt16 = 2,
82 DataInt32 = 4,
83 DataInt64 = 8,
84 DataDouble = 3
85 } data_status;
86
87 InstSeqNum fetch_seq;
88 bool fetch_seq_valid;
89
90 InstSeqNum cp_seq;
91 bool cp_seq_valid;
92
93 struct iRegFile {
94 IntRegFile regs;
95 };
96 iRegFile *iregs;
97 bool regs_valid;
98
99 public:
100 InstRecord(Tick _when, ThreadContext *_thread,
101 const StaticInstPtr &_staticInst,
102 Addr _pc, bool spec)
103 : when(_when), thread(_thread),
104 staticInst(_staticInst), PC(_pc),
105 misspeculating(spec)
106 {
107 data_status = DataInvalid;
108 addr_valid = false;
109 regs_valid = false;
110
111 fetch_seq_valid = false;
112 cp_seq_valid = false;
113 }
114
115 ~InstRecord() { }
116
117 void setAddr(Addr a) { addr = a; addr_valid = true; }
118
119 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
120 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
121 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
122 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
123
124 void setData(int64_t d) { setData((uint64_t)d); }
125 void setData(int32_t d) { setData((uint32_t)d); }
126 void setData(int16_t d) { setData((uint16_t)d); }
127 void setData(int8_t d) { setData((uint8_t)d); }
128
129 void setData(double d) { data.as_double = d; data_status = DataDouble; }
130
131 void setFetchSeq(InstSeqNum seq)
132 { fetch_seq = seq; fetch_seq_valid = true; }
133
134 void setCPSeq(InstSeqNum seq)
135 { cp_seq = seq; cp_seq_valid = true; }
136
137 void setRegs(const IntRegFile ®s);
138
139 void dump();
140};
141
142
143inline void
144InstRecord::setRegs(const IntRegFile ®s)
145{
146 if (!iregs)
147 iregs = new iRegFile;
148
149 std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
150 regs_valid = true;
151}
152
153inline InstRecord *
154getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
155 Addr pc)
156{
157 if (!IsOn(ExecEnable))
158 return NULL;
159
|