1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __EXETRACE_HH__
33#define __EXETRACE_HH__
34
35#include <cstring>
36#include <fstream>
37#include <vector>
38
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __EXETRACE_HH__
33#define __EXETRACE_HH__
34
35#include <cstring>
36#include <fstream>
37#include <vector>
38
|
39#include "sim/host.hh"
40#include "cpu/inst_seq.hh" // for InstSeqNum
| |
41#include "base/trace.hh"
| 39#include "base/trace.hh"
|
42#include "cpu/thread_context.hh"
| 40#include "cpu/inst_seq.hh" // for InstSeqNum
|
43#include "cpu/static_inst.hh"
| 41#include "cpu/static_inst.hh"
|
| 42#include "cpu/thread_context.hh"
43#include "sim/host.hh"
|
44
45class ThreadContext;
46
47
48namespace Trace {
49
| 44
45class ThreadContext;
46
47
48namespace Trace {
49
|
50class InstRecord : public Record
| 50class InstRecord
|
51{
52 protected:
53 typedef TheISA::IntRegFile IntRegFile;
54
| 51{
52 protected:
53 typedef TheISA::IntRegFile IntRegFile;
54
|
| 55 Tick when;
56
|
55 // The following fields are initialized by the constructor and
56 // thus guaranteed to be valid.
57 ThreadContext *thread;
58 // need to make this ref-counted so it doesn't go away before we
59 // dump the record
60 StaticInstPtr staticInst;
61 Addr PC;
62 bool misspeculating;
63
64 // The remaining fields are only valid for particular instruction
65 // types (e.g, addresses for memory ops) or when particular
66 // options are enabled (e.g., tracing full register contents).
67 // Each data field has an associated valid flag to indicate
68 // whether the data field is valid.
69 Addr addr;
70 bool addr_valid;
71
72 union {
73 uint64_t as_int;
74 double as_double;
75 } data;
76 enum {
77 DataInvalid = 0,
78 DataInt8 = 1, // set to equal number of bytes
79 DataInt16 = 2,
80 DataInt32 = 4,
81 DataInt64 = 8,
82 DataDouble = 3
83 } data_status;
84
85 InstSeqNum fetch_seq;
86 bool fetch_seq_valid;
87
88 InstSeqNum cp_seq;
89 bool cp_seq_valid;
90
91 struct iRegFile {
92 IntRegFile regs;
93 };
94 iRegFile *iregs;
95 bool regs_valid;
96
97 public:
| 57 // The following fields are initialized by the constructor and
58 // thus guaranteed to be valid.
59 ThreadContext *thread;
60 // need to make this ref-counted so it doesn't go away before we
61 // dump the record
62 StaticInstPtr staticInst;
63 Addr PC;
64 bool misspeculating;
65
66 // The remaining fields are only valid for particular instruction
67 // types (e.g, addresses for memory ops) or when particular
68 // options are enabled (e.g., tracing full register contents).
69 // Each data field has an associated valid flag to indicate
70 // whether the data field is valid.
71 Addr addr;
72 bool addr_valid;
73
74 union {
75 uint64_t as_int;
76 double as_double;
77 } data;
78 enum {
79 DataInvalid = 0,
80 DataInt8 = 1, // set to equal number of bytes
81 DataInt16 = 2,
82 DataInt32 = 4,
83 DataInt64 = 8,
84 DataDouble = 3
85 } data_status;
86
87 InstSeqNum fetch_seq;
88 bool fetch_seq_valid;
89
90 InstSeqNum cp_seq;
91 bool cp_seq_valid;
92
93 struct iRegFile {
94 IntRegFile regs;
95 };
96 iRegFile *iregs;
97 bool regs_valid;
98
99 public:
|
98 InstRecord(Tick _cycle, ThreadContext *_thread,
| 100 InstRecord(Tick _when, ThreadContext *_thread,
|
99 const StaticInstPtr &_staticInst,
100 Addr _pc, bool spec)
| 101 const StaticInstPtr &_staticInst,
102 Addr _pc, bool spec)
|
101 : Record(_cycle), thread(_thread),
| 103 : when(_when), thread(_thread),
|
102 staticInst(_staticInst), PC(_pc),
103 misspeculating(spec)
104 {
105 data_status = DataInvalid;
106 addr_valid = false;
107 regs_valid = false;
108
109 fetch_seq_valid = false;
110 cp_seq_valid = false;
111 }
112
| 104 staticInst(_staticInst), PC(_pc),
105 misspeculating(spec)
106 {
107 data_status = DataInvalid;
108 addr_valid = false;
109 regs_valid = false;
110
111 fetch_seq_valid = false;
112 cp_seq_valid = false;
113 }
114
|
113 virtual ~InstRecord() { }
| 115 ~InstRecord() { }
|
114
| 116
|
115 virtual void dump(std::ostream &outs);
116
| |
117 void setAddr(Addr a) { addr = a; addr_valid = true; }
118
119 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
120 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
121 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
122 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
123
124 void setData(int64_t d) { setData((uint64_t)d); }
125 void setData(int32_t d) { setData((uint32_t)d); }
126 void setData(int16_t d) { setData((uint16_t)d); }
127 void setData(int8_t d) { setData((uint8_t)d); }
128
129 void setData(double d) { data.as_double = d; data_status = DataDouble; }
130
131 void setFetchSeq(InstSeqNum seq)
132 { fetch_seq = seq; fetch_seq_valid = true; }
133
134 void setCPSeq(InstSeqNum seq)
135 { cp_seq = seq; cp_seq_valid = true; }
136
137 void setRegs(const IntRegFile ®s);
138
| 117 void setAddr(Addr a) { addr = a; addr_valid = true; }
118
119 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
120 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
121 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
122 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
123
124 void setData(int64_t d) { setData((uint64_t)d); }
125 void setData(int32_t d) { setData((uint32_t)d); }
126 void setData(int16_t d) { setData((uint16_t)d); }
127 void setData(int8_t d) { setData((uint8_t)d); }
128
129 void setData(double d) { data.as_double = d; data_status = DataDouble; }
130
131 void setFetchSeq(InstSeqNum seq)
132 { fetch_seq = seq; fetch_seq_valid = true; }
133
134 void setCPSeq(InstSeqNum seq)
135 { cp_seq = seq; cp_seq_valid = true; }
136
137 void setRegs(const IntRegFile ®s);
138
|
139 void finalize() { theLog.append(this); }
| 139 void dump();
|
140
141 enum InstExecFlagBits {
142 TRACE_MISSPEC = 0,
| 140
141 enum InstExecFlagBits {
142 TRACE_MISSPEC = 0,
|
143 PRINT_CYCLE,
| 143 PRINT_TICKS,
|
144 PRINT_OP_CLASS,
145 PRINT_THREAD_NUM,
146 PRINT_RESULT_DATA,
147 PRINT_EFF_ADDR,
148 PRINT_INT_REGS,
149 PRINT_FETCH_SEQ,
150 PRINT_CP_SEQ,
151 PRINT_REG_DELTA,
152 PC_SYMBOL,
153 INTEL_FORMAT,
154 LEGION_LOCKSTEP,
155 NUM_BITS
156 };
157
158 static std::vector<bool> flags;
159 static std::string trace_system;
160
161 static void setParams();
162
163 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
164};
165
166
167inline void
168InstRecord::setRegs(const IntRegFile ®s)
169{
170 if (!iregs)
171 iregs = new iRegFile;
172
173 std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
174 regs_valid = true;
175}
176
177inline
178InstRecord *
| 144 PRINT_OP_CLASS,
145 PRINT_THREAD_NUM,
146 PRINT_RESULT_DATA,
147 PRINT_EFF_ADDR,
148 PRINT_INT_REGS,
149 PRINT_FETCH_SEQ,
150 PRINT_CP_SEQ,
151 PRINT_REG_DELTA,
152 PC_SYMBOL,
153 INTEL_FORMAT,
154 LEGION_LOCKSTEP,
155 NUM_BITS
156 };
157
158 static std::vector<bool> flags;
159 static std::string trace_system;
160
161 static void setParams();
162
163 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
164};
165
166
167inline void
168InstRecord::setRegs(const IntRegFile ®s)
169{
170 if (!iregs)
171 iregs = new iRegFile;
172
173 std::memcpy(&iregs->regs, ®s, sizeof(IntRegFile));
174 regs_valid = true;
175}
176
177inline
178InstRecord *
|
179getInstRecord(Tick cycle, ThreadContext *tc,
| 179getInstRecord(Tick when, ThreadContext *tc,
|
180 const StaticInstPtr staticInst,
181 Addr pc)
182{
183 if (DTRACE(InstExec) &&
184 (InstRecord::traceMisspec() || !tc->misspeculating())) {
| 180 const StaticInstPtr staticInst,
181 Addr pc)
182{
183 if (DTRACE(InstExec) &&
184 (InstRecord::traceMisspec() || !tc->misspeculating())) {
|
185 return new InstRecord(cycle, tc, staticInst, pc,
| 185 return new InstRecord(when, tc, staticInst, pc,
|
186 tc->misspeculating());
187 }
188
189 return NULL;
190}
191
192
193}
194
195#endif // __EXETRACE_HH__
| 186 tc->misspeculating());
187 }
188
189 return NULL;
190}
191
192
193}
194
195#endif // __EXETRACE_HH__
|