exetrace.cc (4172:141705d83494) exetrace.cc (4265:ab2fb6202751)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <errno.h>
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
40#include "arch/utility.hh"
41#include "base/loader/symtab.hh"
35#include <fstream>
36#include <iomanip>
37#include <sys/ipc.h>
38#include <sys/shm.h>
39
40#include "arch/regfile.hh"
41#include "arch/utility.hh"
42#include "base/loader/symtab.hh"
43#include "base/socket.hh"
42#include "config/full_system.hh"
43#include "cpu/base.hh"
44#include "cpu/exetrace.hh"
45#include "cpu/static_inst.hh"
46#include "sim/param.hh"
47#include "sim/system.hh"
48
49#if FULL_SYSTEM

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59
60#if THE_ISA == SPARC_ISA && FULL_SYSTEM
61static int diffcount = 0;
62static bool wasMicro = false;
63#endif
64
65namespace Trace {
66SharedData *shared_data = NULL;
44#include "config/full_system.hh"
45#include "cpu/base.hh"
46#include "cpu/exetrace.hh"
47#include "cpu/static_inst.hh"
48#include "sim/param.hh"
49#include "sim/system.hh"
50
51#if FULL_SYSTEM

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61
62#if THE_ISA == SPARC_ISA && FULL_SYSTEM
63static int diffcount = 0;
64static bool wasMicro = false;
65#endif
66
67namespace Trace {
68SharedData *shared_data = NULL;
69ListenSocket *cosim_listener = NULL;
67
68void
69setupSharedData()
70{
71 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
72 if (shmfd < 0)
73 fatal("Couldn't get shared memory fd. Is Legion running?");
74

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144#endif
145
146void
147Trace::InstRecord::dump()
148{
149 ostream &outs = Trace::output();
150
151 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
70
71void
72setupSharedData()
73{
74 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
75 if (shmfd < 0)
76 fatal("Couldn't get shared memory fd. Is Legion running?");
77

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147#endif
148
149void
150Trace::InstRecord::dump()
151{
152 ostream &outs = Trace::output();
153
154 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
155 bool diff = true;
152 if (IsOn(ExecRegDelta))
153 {
156 if (IsOn(ExecRegDelta))
157 {
158 diff = false;
159#ifndef NDEBUG
154#if THE_ISA == SPARC_ISA
160#if THE_ISA == SPARC_ISA
161 static int fd = 0;
155 //Don't print what happens for each micro-op, just print out
156 //once at the last op, and for regular instructions.
157 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
158 {
162 //Don't print what happens for each micro-op, just print out
163 //once at the last op, and for regular instructions.
164 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
165 {
166 if(!cosim_listener)
167 {
168 int port = 8000;
169 cosim_listener = new ListenSocket();
170 while(!cosim_listener->listen(port, true))
171 {
172 DPRINTF(GDBMisc, "Can't bind port %d\n", port);
173 port++;
174 }
175 ccprintf(cerr, "Listening for cosimulator on port %d\n", port);
176 fd = cosim_listener->accept();
177 }
178 char prefix[] = "goli";
179 for(int p = 0; p < 4; p++)
180 {
181 for(int i = 0; i < 8; i++)
182 {
183 uint64_t regVal;
184 int res = read(fd, &regVal, sizeof(regVal));
185 if(res < 0)
186 panic("First read call failed! %s\n", strerror(errno));
187 regVal = TheISA::gtoh(regVal);
188 uint64_t realRegVal = thread->readIntReg(p * 8 + i);
189 if((regVal & 0xffffffffULL) != (realRegVal & 0xffffffffULL))
190 {
191 DPRINTF(ExecRegDelta, "Register %s%d should be %#x but is %#x.\n", prefix[p], i, regVal, realRegVal);
192 diff = true;
193 }
194 //ccprintf(outs, "%s%d m5 = %#x statetrace = %#x\n", prefix[p], i, realRegVal, regVal);
195 }
196 }
197 /*for(int f = 0; f <= 62; f+=2)
198 {
199 uint64_t regVal;
200 int res = read(fd, &regVal, sizeof(regVal));
201 if(res < 0)
202 panic("First read call failed! %s\n", strerror(errno));
203 regVal = TheISA::gtoh(regVal);
204 uint64_t realRegVal = thread->readFloatRegBits(f, 64);
205 if(regVal != realRegVal)
206 {
207 DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
208 }
209 }*/
210 uint64_t regVal;
211 int res = read(fd, &regVal, sizeof(regVal));
212 if(res < 0)
213 panic("First read call failed! %s\n", strerror(errno));
214 regVal = TheISA::gtoh(regVal);
215 uint64_t realRegVal = thread->readNextPC();
216 if(regVal != realRegVal)
217 {
218 DPRINTF(ExecRegDelta, "Register pc should be %#x but is %#x.\n", regVal, realRegVal);
219 diff = true;
220 }
221 res = read(fd, &regVal, sizeof(regVal));
222 if(res < 0)
223 panic("First read call failed! %s\n", strerror(errno));
224 regVal = TheISA::gtoh(regVal);
225 realRegVal = thread->readNextNPC();
226 if(regVal != realRegVal)
227 {
228 DPRINTF(ExecRegDelta, "Register npc should be %#x but is %#x.\n", regVal, realRegVal);
229 diff = true;
230 }
231 res = read(fd, &regVal, sizeof(regVal));
232 if(res < 0)
233 panic("First read call failed! %s\n", strerror(errno));
234 regVal = TheISA::gtoh(regVal);
235 realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
236 if((regVal & 0xF) != (realRegVal & 0xF))
237 {
238 DPRINTF(ExecRegDelta, "Register ccr should be %#x but is %#x.\n", regVal, realRegVal);
239 diff = true;
240 }
241 }
242#endif
243#endif
244#if 0 //THE_ISA == SPARC_ISA
245 //Don't print what happens for each micro-op, just print out
246 //once at the last op, and for regular instructions.
247 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
248 {
159 static uint64_t regs[32] = {
160 0, 0, 0, 0, 0, 0, 0, 0,
161 0, 0, 0, 0, 0, 0, 0, 0,
162 0, 0, 0, 0, 0, 0, 0, 0,
163 0, 0, 0, 0, 0, 0, 0, 0};
164 static uint64_t ccr = 0;
165 static uint64_t y = 0;
166 static uint64_t floats[32];

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205 outs << " F" << dec << (2 * y) << " = " << hex << newVal;
206 floats[y] = newVal;
207 }
208 }
209 outs << dec << endl;
210 }
211#endif
212 }
249 static uint64_t regs[32] = {
250 0, 0, 0, 0, 0, 0, 0, 0,
251 0, 0, 0, 0, 0, 0, 0, 0,
252 0, 0, 0, 0, 0, 0, 0, 0,
253 0, 0, 0, 0, 0, 0, 0, 0};
254 static uint64_t ccr = 0;
255 static uint64_t y = 0;
256 static uint64_t floats[32];

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295 outs << " F" << dec << (2 * y) << " = " << hex << newVal;
296 floats[y] = newVal;
297 }
298 }
299 outs << dec << endl;
300 }
301#endif
302 }
213 else if (IsOn(ExecIntel)) {
303 if(!diff) {
304 } else if (IsOn(ExecIntel)) {
214 ccprintf(outs, "%7d ) ", when);
215 outs << "0x" << hex << PC << ":\t";
216 if (staticInst->isLoad()) {
217 ccprintf(outs, "<RD %#x>", addr);
218 } else if (staticInst->isStore()) {
219 ccprintf(outs, "<WR %#x>", addr);
220 }
221 outs << endl;

--- 483 unchanged lines hidden --- 		305 ccprintf(outs, "%7d ) ", when);
306 outs << "0x" << hex << PC << ":\t";
307 if (staticInst->isLoad()) {
308 ccprintf(outs, "<RD %#x>", addr);
309 } else if (staticInst->isStore()) {
310 ccprintf(outs, "<WR %#x>", addr);
311 }
312 outs << endl;

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