exetrace.cc (4054:3d617b3be4fa) exetrace.cc (4172:141705d83494)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 157 unchanged lines hidden (view full) ---

166 static uint64_t floats[32];
167 uint64_t newVal;
168 static const char * prefixes[4] = {"G", "O", "L", "I"};
169
170 outs << hex;
171 outs << "PC = " << thread->readNextPC();
172 outs << " NPC = " << thread->readNextNPC();
173 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 157 unchanged lines hidden (view full) ---

166 static uint64_t floats[32];
167 uint64_t newVal;
168 static const char * prefixes[4] = {"G", "O", "L", "I"};
169
170 outs << hex;
171 outs << "PC = " << thread->readNextPC();
172 outs << " NPC = " << thread->readNextNPC();
173 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
174 //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
174 //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_CCR);
175 if(newVal != ccr)
176 {
177 outs << " CCR = " << newVal;
178 ccr = newVal;
179 }
180 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
175 if(newVal != ccr)
176 {
177 outs << " CCR = " << newVal;
178 ccr = newVal;
179 }
180 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
181 //newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
181 //newVal = thread->readMiscRegNoEffect(SparcISA::MISCREG_Y);
182 if(newVal != y)
183 {
184 outs << " Y = " << newVal;
185 y = newVal;
186 }
187 for(int y = 0; y < 4; y++)
188 {
189 for(int x = 0; x < 8; x++)

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382 diffIntRegs = true;
383 }
384 }
385 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
386 if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
387 diffFpRegs = true;
388 }
389 }
182 if(newVal != y)
183 {
184 outs << " Y = " << newVal;
185 y = newVal;
186 }
187 for(int y = 0; y < 4; y++)
188 {
189 for(int x = 0; x < 8; x++)

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382 diffIntRegs = true;
383 }
384 }
385 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
386 if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
387 diffFpRegs = true;
388 }
389 }
390 uint64_t oldTl = thread->readMiscReg(MISCREG_TL);
390 uint64_t oldTl = thread->readMiscRegNoEffect(MISCREG_TL);
391 if (oldTl != shared_data->tl)
392 diffTl = true;
393 for (int i = 1; i <= MaxTL; i++) {
391 if (oldTl != shared_data->tl)
392 diffTl = true;
393 for (int i = 1; i <= MaxTL; i++) {
394 thread->setMiscReg(MISCREG_TL, i);
395 if (thread->readMiscReg(MISCREG_TPC) !=
394 thread->setMiscRegNoEffect(MISCREG_TL, i);
395 if (thread->readMiscRegNoEffect(MISCREG_TPC) !=
396 shared_data->tpc[i-1])
397 diffTpc = true;
396 shared_data->tpc[i-1])
397 diffTpc = true;
398 if (thread->readMiscReg(MISCREG_TNPC) !=
398 if (thread->readMiscRegNoEffect(MISCREG_TNPC) !=
399 shared_data->tnpc[i-1])
400 diffTnpc = true;
399 shared_data->tnpc[i-1])
400 diffTnpc = true;
401 if (thread->readMiscReg(MISCREG_TSTATE) !=
401 if (thread->readMiscRegNoEffect(MISCREG_TSTATE) !=
402 shared_data->tstate[i-1])
403 diffTstate = true;
402 shared_data->tstate[i-1])
403 diffTstate = true;
404 if (thread->readMiscReg(MISCREG_TT) !=
404 if (thread->readMiscRegNoEffect(MISCREG_TT) !=
405 shared_data->tt[i-1])
406 diffTt = true;
405 shared_data->tt[i-1])
406 diffTt = true;
407 if (thread->readMiscReg(MISCREG_HTSTATE) !=
407 if (thread->readMiscRegNoEffect(MISCREG_HTSTATE) !=
408 shared_data->htstate[i-1])
409 diffHtstate = true;
410 }
408 shared_data->htstate[i-1])
409 diffHtstate = true;
410 }
411 thread->setMiscReg(MISCREG_TL, oldTl);
411 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
412
412
413 if(shared_data->tba != thread->readMiscReg(MISCREG_TBA))
413 if(shared_data->tba != thread->readMiscRegNoEffect(MISCREG_TBA))
414 diffTba = true;
415 //When the hpstate register is read by an instruction,
416 //legion has bit 11 set. When it's in storage, it doesn't.
417 //Since we don't directly support seperate interpretations
418 //of the registers like that, the bit is always set to 1 and
419 //we just don't compare it. It's not supposed to matter
420 //anyway.
414 diffTba = true;
415 //When the hpstate register is read by an instruction,
416 //legion has bit 11 set. When it's in storage, it doesn't.
417 //Since we don't directly support seperate interpretations
418 //of the registers like that, the bit is always set to 1 and
419 //we just don't compare it. It's not supposed to matter
420 //anyway.
421 if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
421 if((shared_data->hpstate | (1 << 11)) != thread->readMiscRegNoEffect(MISCREG_HPSTATE))
422 diffHpstate = true;
422 diffHpstate = true;
423 if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
423 if(shared_data->htba != thread->readMiscRegNoEffect(MISCREG_HTBA))
424 diffHtba = true;
424 diffHtba = true;
425 if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
425 if(shared_data->pstate != thread->readMiscRegNoEffect(MISCREG_PSTATE))
426 diffPstate = true;
426 diffPstate = true;
427 //if(shared_data->y != thread->readMiscReg(MISCREG_Y))
427 //if(shared_data->y != thread->readMiscRegNoEffect(MISCREG_Y))
428 if(shared_data->y !=
429 thread->readIntReg(NumIntArchRegs + 1))
430 diffY = true;
428 if(shared_data->y !=
429 thread->readIntReg(NumIntArchRegs + 1))
430 diffY = true;
431 if(shared_data->fsr != thread->readMiscReg(MISCREG_FSR)) {
431 if(shared_data->fsr != thread->readMiscRegNoEffect(MISCREG_FSR)) {
432 diffFsr = true;
433 if (mbits(shared_data->fsr, 63,10) ==
432 diffFsr = true;
433 if (mbits(shared_data->fsr, 63,10) ==
434 mbits(thread->readMiscReg(MISCREG_FSR), 63,10)) {
435 thread->setMiscReg(MISCREG_FSR, shared_data->fsr);
434 mbits(thread->readMiscRegNoEffect(MISCREG_FSR), 63,10)) {
435 thread->setMiscRegNoEffect(MISCREG_FSR, shared_data->fsr);
436 diffFsr = false;
437 }
438 }
436 diffFsr = false;
437 }
438 }
439 //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
439 //if(shared_data->ccr != thread->readMiscRegNoEffect(MISCREG_CCR))
440 if(shared_data->ccr !=
441 thread->readIntReg(NumIntArchRegs + 2))
442 diffCcr = true;
440 if(shared_data->ccr !=
441 thread->readIntReg(NumIntArchRegs + 2))
442 diffCcr = true;
443 if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
443 if(shared_data->gl != thread->readMiscRegNoEffect(MISCREG_GL))
444 diffGl = true;
444 diffGl = true;
445 if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
445 if(shared_data->asi != thread->readMiscRegNoEffect(MISCREG_ASI))
446 diffAsi = true;
446 diffAsi = true;
447 if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
447 if(shared_data->pil != thread->readMiscRegNoEffect(MISCREG_PIL))
448 diffPil = true;
448 diffPil = true;
449 if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
449 if(shared_data->cwp != thread->readMiscRegNoEffect(MISCREG_CWP))
450 diffCwp = true;
450 diffCwp = true;
451 //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
451 //if(shared_data->cansave != thread->readMiscRegNoEffect(MISCREG_CANSAVE))
452 if(shared_data->cansave !=
453 thread->readIntReg(NumIntArchRegs + 3))
454 diffCansave = true;
455 //if(shared_data->canrestore !=
452 if(shared_data->cansave !=
453 thread->readIntReg(NumIntArchRegs + 3))
454 diffCansave = true;
455 //if(shared_data->canrestore !=
456 // thread->readMiscReg(MISCREG_CANRESTORE))
456 // thread->readMiscRegNoEffect(MISCREG_CANRESTORE))
457 if(shared_data->canrestore !=
458 thread->readIntReg(NumIntArchRegs + 4))
459 diffCanrestore = true;
457 if(shared_data->canrestore !=
458 thread->readIntReg(NumIntArchRegs + 4))
459 diffCanrestore = true;
460 //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
460 //if(shared_data->otherwin != thread->readMiscRegNoEffect(MISCREG_OTHERWIN))
461 if(shared_data->otherwin !=
462 thread->readIntReg(NumIntArchRegs + 6))
463 diffOtherwin = true;
461 if(shared_data->otherwin !=
462 thread->readIntReg(NumIntArchRegs + 6))
463 diffOtherwin = true;
464 //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
464 //if(shared_data->cleanwin != thread->readMiscRegNoEffect(MISCREG_CLEANWIN))
465 if(shared_data->cleanwin !=
466 thread->readIntReg(NumIntArchRegs + 5))
467 diffCleanwin = true;
468
469 for (int i = 0; i < 64; i++) {
470 if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
471 diffTlb = true;
472 if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))

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564 << "0x" << setw(8) << setfill('0') << hex
565 << shared_data->instruction
566 << legionInst->disassemble(lgnPc, debugSymbolTable)
567 << endl << endl;
568
569 printSectionHeader(outs, "General State");
570 printColumnLabels(outs);
571 printRegPair(outs, "HPstate",
465 if(shared_data->cleanwin !=
466 thread->readIntReg(NumIntArchRegs + 5))
467 diffCleanwin = true;
468
469 for (int i = 0; i < 64; i++) {
470 if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
471 diffTlb = true;
472 if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))

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564 << "0x" << setw(8) << setfill('0') << hex
565 << shared_data->instruction
566 << legionInst->disassemble(lgnPc, debugSymbolTable)
567 << endl << endl;
568
569 printSectionHeader(outs, "General State");
570 printColumnLabels(outs);
571 printRegPair(outs, "HPstate",
572 thread->readMiscReg(MISCREG_HPSTATE),
572 thread->readMiscRegNoEffect(MISCREG_HPSTATE),
573 shared_data->hpstate | (1 << 11));
574 printRegPair(outs, "Htba",
573 shared_data->hpstate | (1 << 11));
574 printRegPair(outs, "Htba",
575 thread->readMiscReg(MISCREG_HTBA),
575 thread->readMiscRegNoEffect(MISCREG_HTBA),
576 shared_data->htba);
577 printRegPair(outs, "Pstate",
576 shared_data->htba);
577 printRegPair(outs, "Pstate",
578 thread->readMiscReg(MISCREG_PSTATE),
578 thread->readMiscRegNoEffect(MISCREG_PSTATE),
579 shared_data->pstate);
580 printRegPair(outs, "Y",
579 shared_data->pstate);
580 printRegPair(outs, "Y",
581 //thread->readMiscReg(MISCREG_Y),
581 //thread->readMiscRegNoEffect(MISCREG_Y),
582 thread->readIntReg(NumIntArchRegs + 1),
583 shared_data->y);
584 printRegPair(outs, "FSR",
582 thread->readIntReg(NumIntArchRegs + 1),
583 shared_data->y);
584 printRegPair(outs, "FSR",
585 thread->readMiscReg(MISCREG_FSR),
585 thread->readMiscRegNoEffect(MISCREG_FSR),
586 shared_data->fsr);
587 printRegPair(outs, "Ccr",
586 shared_data->fsr);
587 printRegPair(outs, "Ccr",
588 //thread->readMiscReg(MISCREG_CCR),
588 //thread->readMiscRegNoEffect(MISCREG_CCR),
589 thread->readIntReg(NumIntArchRegs + 2),
590 shared_data->ccr);
591 printRegPair(outs, "Tl",
589 thread->readIntReg(NumIntArchRegs + 2),
590 shared_data->ccr);
591 printRegPair(outs, "Tl",
592 thread->readMiscReg(MISCREG_TL),
592 thread->readMiscRegNoEffect(MISCREG_TL),
593 shared_data->tl);
594 printRegPair(outs, "Gl",
593 shared_data->tl);
594 printRegPair(outs, "Gl",
595 thread->readMiscReg(MISCREG_GL),
595 thread->readMiscRegNoEffect(MISCREG_GL),
596 shared_data->gl);
597 printRegPair(outs, "Asi",
596 shared_data->gl);
597 printRegPair(outs, "Asi",
598 thread->readMiscReg(MISCREG_ASI),
598 thread->readMiscRegNoEffect(MISCREG_ASI),
599 shared_data->asi);
600 printRegPair(outs, "Pil",
599 shared_data->asi);
600 printRegPair(outs, "Pil",
601 thread->readMiscReg(MISCREG_PIL),
601 thread->readMiscRegNoEffect(MISCREG_PIL),
602 shared_data->pil);
603 printRegPair(outs, "Cwp",
602 shared_data->pil);
603 printRegPair(outs, "Cwp",
604 thread->readMiscReg(MISCREG_CWP),
604 thread->readMiscRegNoEffect(MISCREG_CWP),
605 shared_data->cwp);
606 printRegPair(outs, "Cansave",
605 shared_data->cwp);
606 printRegPair(outs, "Cansave",
607 //thread->readMiscReg(MISCREG_CANSAVE),
607 //thread->readMiscRegNoEffect(MISCREG_CANSAVE),
608 thread->readIntReg(NumIntArchRegs + 3),
609 shared_data->cansave);
610 printRegPair(outs, "Canrestore",
608 thread->readIntReg(NumIntArchRegs + 3),
609 shared_data->cansave);
610 printRegPair(outs, "Canrestore",
611 //thread->readMiscReg(MISCREG_CANRESTORE),
611 //thread->readMiscRegNoEffect(MISCREG_CANRESTORE),
612 thread->readIntReg(NumIntArchRegs + 4),
613 shared_data->canrestore);
614 printRegPair(outs, "Otherwin",
612 thread->readIntReg(NumIntArchRegs + 4),
613 shared_data->canrestore);
614 printRegPair(outs, "Otherwin",
615 //thread->readMiscReg(MISCREG_OTHERWIN),
615 //thread->readMiscRegNoEffect(MISCREG_OTHERWIN),
616 thread->readIntReg(NumIntArchRegs + 6),
617 shared_data->otherwin);
618 printRegPair(outs, "Cleanwin",
616 thread->readIntReg(NumIntArchRegs + 6),
617 shared_data->otherwin);
618 printRegPair(outs, "Cleanwin",
619 //thread->readMiscReg(MISCREG_CLEANWIN),
619 //thread->readMiscRegNoEffect(MISCREG_CLEANWIN),
620 thread->readIntReg(NumIntArchRegs + 5),
621 shared_data->cleanwin);
622 outs << endl;
623 for (int i = 1; i <= MaxTL; i++) {
624 printLevelHeader(outs, i);
625 printColumnLabels(outs);
620 thread->readIntReg(NumIntArchRegs + 5),
621 shared_data->cleanwin);
622 outs << endl;
623 for (int i = 1; i <= MaxTL; i++) {
624 printLevelHeader(outs, i);
625 printColumnLabels(outs);
626 thread->setMiscReg(MISCREG_TL, i);
626 thread->setMiscRegNoEffect(MISCREG_TL, i);
627 printRegPair(outs, "Tpc",
627 printRegPair(outs, "Tpc",
628 thread->readMiscReg(MISCREG_TPC),
628 thread->readMiscRegNoEffect(MISCREG_TPC),
629 shared_data->tpc[i-1]);
630 printRegPair(outs, "Tnpc",
629 shared_data->tpc[i-1]);
630 printRegPair(outs, "Tnpc",
631 thread->readMiscReg(MISCREG_TNPC),
631 thread->readMiscRegNoEffect(MISCREG_TNPC),
632 shared_data->tnpc[i-1]);
633 printRegPair(outs, "Tstate",
632 shared_data->tnpc[i-1]);
633 printRegPair(outs, "Tstate",
634 thread->readMiscReg(MISCREG_TSTATE),
634 thread->readMiscRegNoEffect(MISCREG_TSTATE),
635 shared_data->tstate[i-1]);
636 printRegPair(outs, "Tt",
635 shared_data->tstate[i-1]);
636 printRegPair(outs, "Tt",
637 thread->readMiscReg(MISCREG_TT),
637 thread->readMiscRegNoEffect(MISCREG_TT),
638 shared_data->tt[i-1]);
639 printRegPair(outs, "Htstate",
638 shared_data->tt[i-1]);
639 printRegPair(outs, "Htstate",
640 thread->readMiscReg(MISCREG_HTSTATE),
640 thread->readMiscRegNoEffect(MISCREG_HTSTATE),
641 shared_data->htstate[i-1]);
642 }
641 shared_data->htstate[i-1]);
642 }
643 thread->setMiscReg(MISCREG_TL, oldTl);
643 thread->setMiscRegNoEffect(MISCREG_TL, oldTl);
644 outs << endl;
645
646 printSectionHeader(outs, "General Purpose Registers");
647 static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
648 for(int y = 0; y < 4; y++) {
649 for(int x = 0; x < 8; x++) {
650 char label[8];
651 sprintf(label, "%s%d", regtypes[y], x);

--- 53 unchanged lines hidden --- 		644 outs << endl;
645
646 printSectionHeader(outs, "General Purpose Registers");
647 static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
648 for(int y = 0; y < 4; y++) {
649 for(int x = 0; x < 8; x++) {
650 char label[8];
651 sprintf(label, "%s%d", regtypes[y], x);

--- 53 unchanged lines hidden ---