exetrace.cc (4046:ef34b290091e) | exetrace.cc (4054:3d617b3be4fa) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 60#if THE_ISA == SPARC_ISA && FULL_SYSTEM 61static int diffcount = 0; 62static bool wasMicro = false; 63#endif 64 65namespace Trace { 66SharedData *shared_data = NULL; | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 60#if THE_ISA == SPARC_ISA && FULL_SYSTEM 61static int diffcount = 0; 62static bool wasMicro = false; 63#endif 64 65namespace Trace { 66SharedData *shared_data = NULL; |
67 68void 69setupSharedData() 70{ 71 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 72 if (shmfd < 0) 73 fatal("Couldn't get shared memory fd. Is Legion running?"); 74 75 shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 76 if (shared_data == (SharedData*)-1) 77 fatal("Couldn't allocate shared memory"); 78 79 if (shared_data->flags != OWN_M5) 80 fatal("Shared memory has invalid owner"); 81 82 if (shared_data->version != VERSION) 83 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 84 shared_data->version); 85 86 // step legion forward one cycle so we can get register values 87 shared_data->flags = OWN_LEGION; |
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67} 68 69//////////////////////////////////////////////////////////////////////// 70// 71// Methods for the InstRecord object 72// 73 74#if THE_ISA == SPARC_ISA --- 48 unchanged lines hidden (view full) --- 123#endif 124 125void 126Trace::InstRecord::dump() 127{ 128 ostream &outs = Trace::output(); 129 130 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); | 88} 89 90//////////////////////////////////////////////////////////////////////// 91// 92// Methods for the InstRecord object 93// 94 95#if THE_ISA == SPARC_ISA --- 48 unchanged lines hidden (view full) --- 144#endif 145 146void 147Trace::InstRecord::dump() 148{ 149 ostream &outs = Trace::output(); 150 151 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); |
131 if (flags[PRINT_REG_DELTA]) | 152 if (IsOn(ExecRegDelta)) |
132 { 133#if THE_ISA == SPARC_ISA 134 //Don't print what happens for each micro-op, just print out 135 //once at the last op, and for regular instructions. 136 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 137 { 138 static uint64_t regs[32] = { 139 0, 0, 0, 0, 0, 0, 0, 0, --- 44 unchanged lines hidden (view full) --- 184 outs << " F" << dec << (2 * y) << " = " << hex << newVal; 185 floats[y] = newVal; 186 } 187 } 188 outs << dec << endl; 189 } 190#endif 191 } | 153 { 154#if THE_ISA == SPARC_ISA 155 //Don't print what happens for each micro-op, just print out 156 //once at the last op, and for regular instructions. 157 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 158 { 159 static uint64_t regs[32] = { 160 0, 0, 0, 0, 0, 0, 0, 0, --- 44 unchanged lines hidden (view full) --- 205 outs << " F" << dec << (2 * y) << " = " << hex << newVal; 206 floats[y] = newVal; 207 } 208 } 209 outs << dec << endl; 210 } 211#endif 212 } |
192 else if (flags[INTEL_FORMAT]) { 193#if FULL_SYSTEM 194 bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system); 195#else 196 bool is_trace_system = true; 197#endif 198 if (is_trace_system) { 199 ccprintf(outs, "%7d ) ", when); 200 outs << "0x" << hex << PC << ":\t"; 201 if (staticInst->isLoad()) { 202 outs << "<RD 0x" << hex << addr; 203 outs << ">"; 204 } else if (staticInst->isStore()) { 205 outs << "<WR 0x" << hex << addr; 206 outs << ">"; 207 } 208 outs << endl; | 213 else if (IsOn(ExecIntel)) { 214 ccprintf(outs, "%7d ) ", when); 215 outs << "0x" << hex << PC << ":\t"; 216 if (staticInst->isLoad()) { 217 ccprintf(outs, "<RD %#x>", addr); 218 } else if (staticInst->isStore()) { 219 ccprintf(outs, "<WR %#x>", addr); |
209 } | 220 } |
221 outs << endl; |
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210 } else { | 222 } else { |
211 if (flags[PRINT_TICKS]) | 223 if (IsOn(ExecTicks)) |
212 ccprintf(outs, "%7d: ", when); 213 214 outs << thread->getCpuPtr()->name() << " "; 215 | 224 ccprintf(outs, "%7d: ", when); 225 226 outs << thread->getCpuPtr()->name() << " "; 227 |
216 if (flags[TRACE_MISSPEC]) | 228 if (IsOn(ExecSpeculative)) |
217 outs << (misspeculating ? "-" : "+") << " "; 218 | 229 outs << (misspeculating ? "-" : "+") << " "; 230 |
219 if (flags[PRINT_THREAD_NUM]) | 231 if (IsOn(ExecThread)) |
220 outs << "T" << thread->getThreadNum() << " : "; 221 222 223 std::string sym_str; 224 Addr sym_addr; 225 if (debugSymbolTable 226 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) | 232 outs << "T" << thread->getThreadNum() << " : "; 233 234 235 std::string sym_str; 236 Addr sym_addr; 237 if (debugSymbolTable 238 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) |
227 && flags[PC_SYMBOL]) { | 239 && IsOn(ExecSymbol)) { |
228 if (PC != sym_addr) 229 sym_str += csprintf("+%d", PC - sym_addr); 230 outs << "@" << sym_str << " : "; 231 } 232 else { 233 outs << "0x" << hex << PC << " : "; 234 } 235 --- 9 unchanged lines hidden (view full) --- 245 mc += " "; 246 outs << mc; 247#else 248 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 249#endif 250 251 outs << " : "; 252 | 240 if (PC != sym_addr) 241 sym_str += csprintf("+%d", PC - sym_addr); 242 outs << "@" << sym_str << " : "; 243 } 244 else { 245 outs << "0x" << hex << PC << " : "; 246 } 247 --- 9 unchanged lines hidden (view full) --- 257 mc += " "; 258 outs << mc; 259#else 260 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 261#endif 262 263 outs << " : "; 264 |
253 if (flags[PRINT_OP_CLASS]) { | 265 if (IsOn(ExecOpClass)) { |
254 outs << opClassStrings[staticInst->opClass()] << " : "; 255 } 256 | 266 outs << opClassStrings[staticInst->opClass()] << " : "; 267 } 268 |
257 if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) { | 269 if (IsOn(ExecResult) && data_status != DataInvalid) { |
258 outs << " D="; 259#if 0 260 if (data_status == DataDouble) 261 ccprintf(outs, "%f", data.as_double); 262 else 263 ccprintf(outs, "%#018x", data.as_int); 264#else 265 ccprintf(outs, "%#018x", data.as_int); 266#endif 267 } 268 | 270 outs << " D="; 271#if 0 272 if (data_status == DataDouble) 273 ccprintf(outs, "%f", data.as_double); 274 else 275 ccprintf(outs, "%#018x", data.as_int); 276#else 277 ccprintf(outs, "%#018x", data.as_int); 278#endif 279 } 280 |
269 if (flags[PRINT_EFF_ADDR] && addr_valid) | 281 if (IsOn(ExecEffAddr) && addr_valid) |
270 outs << " A=0x" << hex << addr; 271 | 282 outs << " A=0x" << hex << addr; 283 |
272 if (flags[PRINT_INT_REGS] && regs_valid) { | 284 if (IsOn(ExecIntRegs) && regs_valid) { |
273 for (int i = 0; i < TheISA::NumIntRegs;) 274 for (int j = i + 1; i <= j; i++) 275 ccprintf(outs, "r%02d = %#018x%s", i, 276 iregs->regs.readReg(i), 277 ((i == j) ? "\n" : " ")); 278 outs << "\n"; 279 } 280 | 285 for (int i = 0; i < TheISA::NumIntRegs;) 286 for (int j = i + 1; i <= j; i++) 287 ccprintf(outs, "r%02d = %#018x%s", i, 288 iregs->regs.readReg(i), 289 ((i == j) ? "\n" : " ")); 290 outs << "\n"; 291 } 292 |
281 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid) | 293 if (IsOn(ExecFetchSeq) && fetch_seq_valid) |
282 outs << " FetchSeq=" << dec << fetch_seq; 283 | 294 outs << " FetchSeq=" << dec << fetch_seq; 295 |
284 if (flags[PRINT_CP_SEQ] && cp_seq_valid) | 296 if (IsOn(ExecCPSeq) && cp_seq_valid) |
285 outs << " CPSeq=" << dec << cp_seq; 286 287 // 288 // End of line... 289 // 290 outs << endl; 291 } 292#if THE_ISA == SPARC_ISA && FULL_SYSTEM 293 // Compare | 297 outs << " CPSeq=" << dec << cp_seq; 298 299 // 300 // End of line... 301 // 302 outs << endl; 303 } 304#if THE_ISA == SPARC_ISA && FULL_SYSTEM 305 // Compare |
294 if (flags[LEGION_LOCKSTEP]) | 306 if (IsOn(ExecLegion)) |
295 { 296 bool compared = false; 297 bool diffPC = false; 298 bool diffCC = false; 299 bool diffInst = false; 300 bool diffIntRegs = false; 301 bool diffFpRegs = false; 302 bool diffTpc = false; --- 15 unchanged lines hidden (view full) --- 318 bool diffCwp = false; 319 bool diffCansave = false; 320 bool diffCanrestore = false; 321 bool diffOtherwin = false; 322 bool diffCleanwin = false; 323 bool diffTlb = false; 324 Addr m5Pc, lgnPc; 325 | 307 { 308 bool compared = false; 309 bool diffPC = false; 310 bool diffCC = false; 311 bool diffInst = false; 312 bool diffIntRegs = false; 313 bool diffFpRegs = false; 314 bool diffTpc = false; --- 15 unchanged lines hidden (view full) --- 330 bool diffCwp = false; 331 bool diffCansave = false; 332 bool diffCanrestore = false; 333 bool diffOtherwin = false; 334 bool diffCleanwin = false; 335 bool diffTlb = false; 336 Addr m5Pc, lgnPc; 337 |
338 if (!shared_data) 339 setupSharedData(); 340 |
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326 // We took a trap on a micro-op... 327 if (wasMicro && !staticInst->isMicroOp()) 328 { 329 // let's skip comparing this tick 330 while (!compared) 331 if (shared_data->flags == OWN_M5) { 332 shared_data->flags = OWN_LEGION; 333 compared = true; --- 347 unchanged lines hidden (view full) --- 681 shared_data->flags = OWN_LEGION; 682 } 683 } // while 684 } // if not microop 685 } 686#endif 687} 688 | 341 // We took a trap on a micro-op... 342 if (wasMicro && !staticInst->isMicroOp()) 343 { 344 // let's skip comparing this tick 345 while (!compared) 346 if (shared_data->flags == OWN_M5) { 347 shared_data->flags = OWN_LEGION; 348 compared = true; --- 347 unchanged lines hidden (view full) --- 696 shared_data->flags = OWN_LEGION; 697 } 698 } // while 699 } // if not microop 700 } 701#endif 702} 703 |
689 690vector<bool> Trace::InstRecord::flags(NUM_BITS); 691string Trace::InstRecord::trace_system; 692 693//////////////////////////////////////////////////////////////////////// 694// 695// Parameter space for per-cycle execution address tracing options. 696// Derive from ParamContext so we can override checkParams() function. 697// 698class ExecutionTraceParamContext : public ParamContext 699{ 700 public: 701 ExecutionTraceParamContext(const string &_iniSection) 702 : ParamContext(_iniSection) 703 { 704 } 705 706 void checkParams(); // defined at bottom of file 707}; 708 709ExecutionTraceParamContext exeTraceParams("exetrace"); 710 711Param<bool> exe_trace_spec(&exeTraceParams, "speculative", 712 "capture speculative instructions", true); 713 714Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle", 715 "print cycle number", true); 716Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass", 717 "print op class", true); 718Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread", 719 "print thread number", true); 720Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr", 721 "print effective address", true); 722Param<bool> exe_trace_print_data(&exeTraceParams, "print_data", 723 "print result data", true); 724Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs", 725 "print all integer regs", false); 726Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq", 727 "print fetch sequence number", false); 728Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq", 729 "print correct-path sequence number", false); 730Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta", 731 "print which registers changed to what", false); 732Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol", 733 "Use symbols for the PC if available", true); 734Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format", 735 "print trace in intel compatible format", false); 736Param<bool> exe_trace_legion_lockstep(&exeTraceParams, "legion_lockstep", 737 "Compare sim state to legion state every cycle", 738 false); 739Param<string> exe_trace_system(&exeTraceParams, "trace_system", 740 "print trace of which system (client or server)", 741 "client"); 742 743 744// 745// Helper function for ExecutionTraceParamContext::checkParams() just 746// to get us into the InstRecord namespace 747// 748void 749Trace::InstRecord::setParams() 750{ 751 flags[TRACE_MISSPEC] = exe_trace_spec; 752 753 flags[PRINT_TICKS] = exe_trace_print_cycle; 754 flags[PRINT_OP_CLASS] = exe_trace_print_opclass; 755 flags[PRINT_THREAD_NUM] = exe_trace_print_thread; 756 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr; 757 flags[PRINT_EFF_ADDR] = exe_trace_print_data; 758 flags[PRINT_INT_REGS] = exe_trace_print_iregs; 759 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq; 760 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq; 761 flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta; 762 flags[PC_SYMBOL] = exe_trace_pc_symbol; 763 flags[INTEL_FORMAT] = exe_trace_intel_format; 764 flags[LEGION_LOCKSTEP] = exe_trace_legion_lockstep; 765 trace_system = exe_trace_system; 766 767 // If were going to be in lockstep with Legion 768 // Setup shared memory, and get otherwise ready 769 if (flags[LEGION_LOCKSTEP]) { 770 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 771 if (shmfd < 0) 772 fatal("Couldn't get shared memory fd. Is Legion running?"); 773 774 shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 775 if (shared_data == (SharedData*)-1) 776 fatal("Couldn't allocate shared memory"); 777 778 if (shared_data->flags != OWN_M5) 779 fatal("Shared memory has invalid owner"); 780 781 if (shared_data->version != VERSION) 782 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 783 shared_data->version); 784 785 // step legion forward one cycle so we can get register values 786 shared_data->flags = OWN_LEGION; 787 } 788} 789 790void 791ExecutionTraceParamContext::checkParams() 792{ 793 Trace::InstRecord::setParams(); 794} 795 | 704/* namespace Trace */ } |