exetrace.cc (3506:99f86646ba5c) exetrace.cc (3584:8c3cdb2c001c)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32 */
33
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32 */
33
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
40#include "arch/utility.hh"
40#include "base/loader/symtab.hh"
41#include "cpu/base.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/static_inst.hh"
44#include "sim/param.hh"
45#include "sim/system.hh"
46
47//XXX This is temporary

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226 if (flags[PRINT_CP_SEQ] && cp_seq_valid)
227 outs << " CPSeq=" << dec << cp_seq;
228
229 //
230 // End of line...
231 //
232 outs << endl;
233 }
41#include "base/loader/symtab.hh"
42#include "cpu/base.hh"
43#include "cpu/exetrace.hh"
44#include "cpu/static_inst.hh"
45#include "sim/param.hh"
46#include "sim/system.hh"
47
48//XXX This is temporary

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227 if (flags[PRINT_CP_SEQ] && cp_seq_valid)
228 outs << " CPSeq=" << dec << cp_seq;
229
230 //
231 // End of line...
232 //
233 outs << endl;
234 }
235#if THE_ISA == SPARC_ISA
234 // Compare
235 if (flags[LEGION_LOCKSTEP])
236 {
237 bool compared = false;
238 bool diffPC = false;
239 bool diffInst = false;
240 bool diffRegs = false;
241
236 // Compare
237 if (flags[LEGION_LOCKSTEP])
238 {
239 bool compared = false;
240 bool diffPC = false;
241 bool diffInst = false;
242 bool diffRegs = false;
243
242 while (!compared) {
243 if (shared_data->flags == OWN_M5) {
244 if (shared_data->pc != PC)
245 diffPC = true;
246 if (shared_data->instruction != staticInst->machInst)
247 diffInst = true;
248 for (int i = 0; i < TheISA::NumIntRegs; i++) {
249 if (thread->readIntReg(i) != shared_data->intregs[i])
250 diffRegs = true;
251 }
244 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
245 while (!compared) {
246 if (shared_data->flags == OWN_M5) {
247 if (shared_data->pc != PC)
248 diffPC = true;
249 if (shared_data->instruction != staticInst->machInst)
250 diffInst = true;
251 for (int i = 0; i < TheISA::NumIntRegs; i++) {
252 if (thread->readIntReg(i) != shared_data->intregs[i])
253 diffRegs = true;
254 }
252
255
253 if (diffPC || diffInst || diffRegs ) {
254 outs << "Differences found between M5 and Legion:";
255 if (diffPC)
256 outs << " PC";
257 if (diffInst)
258 outs << " Instruction";
259 if (diffRegs)
260 outs << " IntRegs";
261 outs << endl;
256 if (diffPC || diffInst || diffRegs ) {
257 outs << "Differences found between M5 and Legion:";
258 if (diffPC)
259 outs << " [PC]";
260 if (diffInst)
261 outs << " [Instruction]";
262 if (diffRegs)
263 outs << " [IntRegs]";
264 outs << endl << endl;;
262
265
263 outs << "M5 PC: " << setw(20) << "0x" << hex << PC;
264 outs << "Legion PC: " << setw(20) << "0x" << hex <<
265 shared_data->pc << endl;
266 outs << setfill(' ') << setw(15)
267 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
268 << hex << PC << endl;
269 outs << setfill(' ') << setw(15)
270 << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
271 << shared_data->pc << endl << endl;
266
272
273 outs << setfill(' ') << setw(15)
274 << "M5 Inst: " << "0x"<< setw(8)
275 << setfill('0') << hex << staticInst->machInst
276 << staticInst->disassemble(PC, debugSymbolTable)
277 << endl;
267
278
279 StaticInstPtr legionInst = StaticInst::decode(makeExtMI(shared_data->instruction, thread));
280 outs << setfill(' ') << setw(15)
281 << " Legion Inst: "
282 << "0x" << setw(8) << setfill('0') << hex
283 << shared_data->instruction
284 << legionInst->disassemble(shared_data->pc, debugSymbolTable)
285 << endl;
268
286
269 outs << "M5 Instruction: " << staticInst->machInst << "("
270 << staticInst->disassemble(PC, debugSymbolTable)
271 << ")" << "Legion Instruction: " <<
272 shared_data->instruction << "("
273 /*<< legionInst->disassemble(shared_data->pc,
274 debugSymbolTable)*/
275 << ")" << endl;
276
277 for (int i = 0; i < TheISA::NumIntRegs; i++) {
278 outs << setw(16) << "0x" << hex << thread->readIntReg(i)
279 << setw(16) << "0x" << hex << shared_data->intregs[i];
280
281 if (thread->readIntReg(i) != shared_data->intregs[i])
282 outs << "<--- Different";
283 outs << endl;
287 outs << endl;
288
289 static const char * regtypes[4] = {"%g", "%o", "%l", "%i"};
290 for(int y = 0; y < 4; y++)
291 {
292 for(int x = 0; x < 8; x++)
293 {
294 outs << regtypes[y] << x << " " ;
295 outs << "0x" << hex << setw(16) << thread->readIntReg(y*8+x);
296 if (thread->readIntReg(y*8 + x) != shared_data->intregs[y*8+x])
297 outs << " X ";
298 else
299 outs << " | ";
300 outs << "0x" << setw(16) << hex << shared_data->intregs[y*8+x]
301 << endl;
302 }
303 }
304 fatal("Differences found between Legion and M5\n");
284 }
305 }
285 }
286
306
287 compared = true;
288 shared_data->flags = OWN_LEGION;
289 }
290 }
291
307 compared = true;
308 shared_data->flags = OWN_LEGION;
309 }
310 } // while
311 } // if not microop
292 }
312 }
313#endif
293}
294
295
296vector<bool> Trace::InstRecord::flags(NUM_BITS);
297string Trace::InstRecord::trace_system;
298
299////////////////////////////////////////////////////////////////////////
300//

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315
316
317vector<bool> Trace::InstRecord::flags(NUM_BITS);
318string Trace::InstRecord::trace_system;
319
320////////////////////////////////////////////////////////////////////////
321//

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