1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36
37#include "base/loader/symtab.hh"
38#include "cpu/base.hh"
39#include "cpu/exetrace.hh"
40#include "cpu/static_inst.hh"
41#include "sim/param.hh"
42#include "sim/system.hh"
43
44using namespace std;
45
46
47////////////////////////////////////////////////////////////////////////
48//
49// Methods for the InstRecord object
50//
51
52
53void
54Trace::InstRecord::dump(ostream &outs)
55{
56 if (flags[INTEL_FORMAT]) {
57#if FULL_SYSTEM
58 bool is_trace_system = (cpu->system->name() == trace_system);
59#else
60 bool is_trace_system = true;
61#endif
62 if (is_trace_system) {
63 ccprintf(outs, "%7d ) ", cycle);
64 outs << "0x" << hex << PC << ":\t";
65 if (staticInst->isLoad()) {
66 outs << "<RD 0x" << hex << addr;
67 outs << ">";
68 } else if (staticInst->isStore()) {
69 outs << "<WR 0x" << hex << addr;
70 outs << ">";
71 }
72 outs << endl;
73 }
74 } else {
75 if (flags[PRINT_CYCLE])
76 ccprintf(outs, "%7d: ", cycle);
77
78 outs << cpu->name() << " ";
79
80 if (flags[TRACE_MISSPEC])
81 outs << (misspeculating ? "-" : "+") << " ";
82
83 if (flags[PRINT_THREAD_NUM])
84 outs << "T" << thread << " : ";
85
86
87 std::string sym_str;
88 Addr sym_addr;
89 if (debugSymbolTable
85 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
86 && flags[PC_SYMBOL]) {
90 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)) {
91 if (PC != sym_addr)
92 sym_str += csprintf("+%d", PC - sym_addr);
93 outs << "@" << sym_str << " : ";
94 }
95 else {
96 outs << "0x" << hex << PC << " : ";
97 }
98
99 //
100 // Print decoded instruction
101 //
102
103#if defined(__GNUC__) && (__GNUC__ < 3)
104 // There's a bug in gcc 2.x library that prevents setw()
105 // from working properly on strings
106 string mc(staticInst->disassemble(PC, debugSymbolTable));
107 while (mc.length() < 26)
108 mc += " ";
109 outs << mc;
110#else
111 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
112#endif
113
114 outs << " : ";
115
116 if (flags[PRINT_OP_CLASS]) {
117 outs << opClassStrings[staticInst->opClass()] << " : ";
118 }
119
120 if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
121 outs << " D=";
122#if 0
123 if (data_status == DataDouble)
124 ccprintf(outs, "%f", data.as_double);
125 else
126 ccprintf(outs, "%#018x", data.as_int);
127#else
128 ccprintf(outs, "%#018x", data.as_int);
129#endif
130 }
131
132 if (flags[PRINT_EFF_ADDR] && addr_valid)
133 outs << " A=0x" << hex << addr;
134
135 if (flags[PRINT_INT_REGS] && regs_valid) {
136 for (int i = 0; i < TheISA::NumIntRegs;)
137 for (int j = i + 1; i <= j; i++)
138 ccprintf(outs, "r%02d = %#018x%s", i,
139 iregs->regs.readReg(i),
140 ((i == j) ? "\n" : " "));
141 outs << "\n";
142 }
143
144 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
145 outs << " FetchSeq=" << dec << fetch_seq;
146
147 if (flags[PRINT_CP_SEQ] && cp_seq_valid)
148 outs << " CPSeq=" << dec << cp_seq;
149
150 //
151 // End of line...
152 //
153 outs << endl;
154 }
155}
156
157
158vector<bool> Trace::InstRecord::flags(NUM_BITS);
159string Trace::InstRecord::trace_system;
160
161////////////////////////////////////////////////////////////////////////
162//
163// Parameter space for per-cycle execution address tracing options.
164// Derive from ParamContext so we can override checkParams() function.
165//
166class ExecutionTraceParamContext : public ParamContext
167{
168 public:
169 ExecutionTraceParamContext(const string &_iniSection)
170 : ParamContext(_iniSection)
171 {
172 }
173
174 void checkParams(); // defined at bottom of file
175};
176
177ExecutionTraceParamContext exeTraceParams("exetrace");
178
179Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
180 "capture speculative instructions", true);
181
182Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
183 "print cycle number", true);
184Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
185 "print op class", true);
186Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
187 "print thread number", true);
188Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
189 "print effective address", true);
190Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
191 "print result data", true);
192Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
193 "print all integer regs", false);
194Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
195 "print fetch sequence number", false);
196Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
197 "print correct-path sequence number", false);
194Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
195 "Use symbols for the PC if available", true);
198Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
199 "print trace in intel compatible format", false);
200Param<string> exe_trace_system(&exeTraceParams, "trace_system",
201 "print trace of which system (client or server)",
202 "client");
203
204
205//
206// Helper function for ExecutionTraceParamContext::checkParams() just
207// to get us into the InstRecord namespace
208//
209void
210Trace::InstRecord::setParams()
211{
212 flags[TRACE_MISSPEC] = exe_trace_spec;
213
214 flags[PRINT_CYCLE] = exe_trace_print_cycle;
215 flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
216 flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
217 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
218 flags[PRINT_EFF_ADDR] = exe_trace_print_data;
219 flags[PRINT_INT_REGS] = exe_trace_print_iregs;
220 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
221 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
220 flags[PC_SYMBOL] = exe_trace_pc_symbol;
222 flags[INTEL_FORMAT] = exe_trace_intel_format;
223 trace_system = exe_trace_system;
224}
225
226void
227ExecutionTraceParamContext::checkParams()
228{
229 Trace::InstRecord::setParams();
230}
231