1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 50 unchanged lines hidden (view full) --- 59 60#if THE_ISA == SPARC_ISA && FULL_SYSTEM 61static int diffcount = 0; 62static bool wasMicro = false; 63#endif 64 65namespace Trace { 66SharedData *shared_data = NULL; |
67 68void 69setupSharedData() 70{ 71 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777); 72 if (shmfd < 0) 73 fatal("Couldn't get shared memory fd. Is Legion running?"); 74 75 shared_data = (SharedData*)shmat(shmfd, NULL, SHM_RND); 76 if (shared_data == (SharedData*)-1) 77 fatal("Couldn't allocate shared memory"); 78 79 if (shared_data->flags != OWN_M5) 80 fatal("Shared memory has invalid owner"); 81 82 if (shared_data->version != VERSION) 83 fatal("Shared Data is wrong version! M5: %d Legion: %d", VERSION, 84 shared_data->version); 85 86 // step legion forward one cycle so we can get register values 87 shared_data->flags = OWN_LEGION; |
88} 89 90//////////////////////////////////////////////////////////////////////// 91// 92// Methods for the InstRecord object 93// 94 95#if THE_ISA == SPARC_ISA --- 48 unchanged lines hidden (view full) --- 144#endif 145 146void 147Trace::InstRecord::dump() 148{ 149 ostream &outs = Trace::output(); 150 151 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst); |
152 if (IsOn(ExecRegDelta)) |
153 { 154#if THE_ISA == SPARC_ISA 155 //Don't print what happens for each micro-op, just print out 156 //once at the last op, and for regular instructions. 157 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) 158 { 159 static uint64_t regs[32] = { 160 0, 0, 0, 0, 0, 0, 0, 0, --- 44 unchanged lines hidden (view full) --- 205 outs << " F" << dec << (2 * y) << " = " << hex << newVal; 206 floats[y] = newVal; 207 } 208 } 209 outs << dec << endl; 210 } 211#endif 212 } |
213 else if (IsOn(ExecIntel)) { 214 ccprintf(outs, "%7d ) ", when); 215 outs << "0x" << hex << PC << ":\t"; 216 if (staticInst->isLoad()) { 217 ccprintf(outs, "<RD %#x>", addr); 218 } else if (staticInst->isStore()) { 219 ccprintf(outs, "<WR %#x>", addr); |
220 } |
221 outs << endl; |
222 } else { |
223 if (IsOn(ExecTicks)) |
224 ccprintf(outs, "%7d: ", when); 225 226 outs << thread->getCpuPtr()->name() << " "; 227 |
228 if (IsOn(ExecSpeculative)) |
229 outs << (misspeculating ? "-" : "+") << " "; 230 |
231 if (IsOn(ExecThread)) |
232 outs << "T" << thread->getThreadNum() << " : "; 233 234 235 std::string sym_str; 236 Addr sym_addr; 237 if (debugSymbolTable 238 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr) |
239 && IsOn(ExecSymbol)) { |
240 if (PC != sym_addr) 241 sym_str += csprintf("+%d", PC - sym_addr); 242 outs << "@" << sym_str << " : "; 243 } 244 else { 245 outs << "0x" << hex << PC << " : "; 246 } 247 --- 9 unchanged lines hidden (view full) --- 257 mc += " "; 258 outs << mc; 259#else 260 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable); 261#endif 262 263 outs << " : "; 264 |
265 if (IsOn(ExecOpClass)) { |
266 outs << opClassStrings[staticInst->opClass()] << " : "; 267 } 268 |
269 if (IsOn(ExecResult) && data_status != DataInvalid) { |
270 outs << " D="; 271#if 0 272 if (data_status == DataDouble) 273 ccprintf(outs, "%f", data.as_double); 274 else 275 ccprintf(outs, "%#018x", data.as_int); 276#else 277 ccprintf(outs, "%#018x", data.as_int); 278#endif 279 } 280 |
281 if (IsOn(ExecEffAddr) && addr_valid) |
282 outs << " A=0x" << hex << addr; 283 |
284 if (IsOn(ExecIntRegs) && regs_valid) { |
285 for (int i = 0; i < TheISA::NumIntRegs;) 286 for (int j = i + 1; i <= j; i++) 287 ccprintf(outs, "r%02d = %#018x%s", i, 288 iregs->regs.readReg(i), 289 ((i == j) ? "\n" : " ")); 290 outs << "\n"; 291 } 292 |
293 if (IsOn(ExecFetchSeq) && fetch_seq_valid) |
294 outs << " FetchSeq=" << dec << fetch_seq; 295 |
296 if (IsOn(ExecCPSeq) && cp_seq_valid) |
297 outs << " CPSeq=" << dec << cp_seq; 298 299 // 300 // End of line... 301 // 302 outs << endl; 303 } 304#if THE_ISA == SPARC_ISA && FULL_SYSTEM 305 // Compare |
306 if (IsOn(ExecLegion)) |
307 { 308 bool compared = false; 309 bool diffPC = false; 310 bool diffCC = false; 311 bool diffInst = false; 312 bool diffIntRegs = false; 313 bool diffFpRegs = false; 314 bool diffTpc = false; --- 15 unchanged lines hidden (view full) --- 330 bool diffCwp = false; 331 bool diffCansave = false; 332 bool diffCanrestore = false; 333 bool diffOtherwin = false; 334 bool diffCleanwin = false; 335 bool diffTlb = false; 336 Addr m5Pc, lgnPc; 337 |
338 if (!shared_data) 339 setupSharedData(); 340 |
341 // We took a trap on a micro-op... 342 if (wasMicro && !staticInst->isMicroOp()) 343 { 344 // let's skip comparing this tick 345 while (!compared) 346 if (shared_data->flags == OWN_M5) { 347 shared_data->flags = OWN_LEGION; 348 compared = true; --- 347 unchanged lines hidden (view full) --- 696 shared_data->flags = OWN_LEGION; 697 } 698 } // while 699 } // if not microop 700 } 701#endif 702} 703 |
704/* namespace Trace */ } |