1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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136 static uint64_t y = 0;
137 static uint64_t floats[32];
138 uint64_t newVal;
139 static const char * prefixes[4] = {"G", "O", "L", "I"};
140
141 outs << hex;
142 outs << "PC = " << thread->readNextPC();
143 outs << " NPC = " << thread->readNextNPC();
144 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
145 //newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
144 newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
145 if(newVal != ccr)
146 {
147 outs << " CCR = " << newVal;
148 ccr = newVal;
149 }
151 newVal = thread->readIntReg(SparcISA::NumIntArchRegs + 1);
152 //newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
150 newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
151 if(newVal != y)
152 {
153 outs << " Y = " << newVal;
154 y = newVal;
155 }
156 for(int y = 0; y < 4; y++)
157 {
158 for(int x = 0; x < 8; x++)

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280 outs << endl;
281 }
282#if THE_ISA == SPARC_ISA
283 // Compare
284 if (flags[LEGION_LOCKSTEP])
285 {
286 bool compared = false;
287 bool diffPC = false;
288 bool diffCC = false;
289 bool diffInst = false;
290 bool diffRegs = false;
291 bool diffTpc = false;
292 bool diffTnpc = false;
293 bool diffTstate = false;
294 bool diffTt = false;
295 bool diffTba = false;
296 bool diffHpstate = false;

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313
314 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp()) {
315 while (!compared) {
316 if (shared_data->flags == OWN_M5) {
317 m5Pc = PC & TheISA::PAddrImplMask;
318 lgnPc = shared_data->pc & TheISA::PAddrImplMask;
319 if (lgnPc != m5Pc)
320 diffPC = true;
321
322 if (shared_data->cycle_count !=
323 thread->getCpuPtr()->instCount())
324 diffCC = true;
325
326 if (shared_data->instruction !=
327 (SparcISA::MachInst)staticInst->machInst) {
328 diffInst = true;
329 }
330 for (int i = 0; i < TheISA::NumIntArchRegs; i++) {
331 if (thread->readIntReg(i) != shared_data->intregs[i]) {
332 diffRegs = true;
333 }

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364 //we just don't compare it. It's not supposed to matter
365 //anyway.
366 if((shared_data->hpstate | (1 << 11)) != thread->readMiscReg(MISCREG_HPSTATE))
367 diffHpstate = true;
368 if(shared_data->htba != thread->readMiscReg(MISCREG_HTBA))
369 diffHtba = true;
370 if(shared_data->pstate != thread->readMiscReg(MISCREG_PSTATE))
371 diffPstate = true;
368 //if(shared_data->y != thread->readMiscReg(MISCREG_Y))
369 if(shared_data->y !=
370 thread->readIntReg(NumIntArchRegs + 1))
372 if(shared_data->y != thread->readMiscReg(MISCREG_Y))
373 diffY = true;
372 //if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
373 if(shared_data->ccr !=
374 thread->readIntReg(NumIntArchRegs + 2))
374 if(shared_data->ccr != thread->readMiscReg(MISCREG_CCR))
375 diffCcr = true;
376 if(shared_data->gl != thread->readMiscReg(MISCREG_GL))
377 diffGl = true;
378 if(shared_data->asi != thread->readMiscReg(MISCREG_ASI))
379 diffAsi = true;
380 if(shared_data->pil != thread->readMiscReg(MISCREG_PIL))
381 diffPil = true;
382 if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
383 diffCwp = true;
384 //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
385 if(shared_data->cansave !=
386 thread->readIntReg(NumIntArchRegs + 3))
384 if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
385 diffCansave = true;
388 //if(shared_data->canrestore !=
389 // thread->readMiscReg(MISCREG_CANRESTORE))
386 if(shared_data->canrestore !=
391 thread->readMiscReg(NumIntArchRegs + 4))
387 thread->readMiscReg(MISCREG_CANRESTORE))
388 diffCanrestore = true;
393 //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
394 if(shared_data->otherwin !=
395 thread->readIntReg(NumIntArchRegs + 5))
389 if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
390 diffOtherwin = true;
397 //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
398 if(shared_data->cleanwin !=
399 thread->readMiscReg(NumIntArchRegs + 6))
391 if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
392 diffCleanwin = true;
393
402 if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc ||
403 diffTstate || diffTt || diffHpstate ||
394 if (diffPC || diffCC || diffInst || diffRegs || diffTpc ||
395 diffTnpc || diffTstate || diffTt || diffHpstate ||
396 diffHtstate || diffHtba || diffPstate || diffY ||
397 diffCcr || diffTl || diffGl || diffAsi || diffPil ||
398 diffCwp || diffCansave || diffCanrestore ||
399 diffOtherwin || diffCleanwin) {
400 outs << "Differences found between M5 and Legion:";
401 if (diffPC)
402 outs << " [PC]";
403 if (diffCC)
404 outs << " [CC]";
405 if (diffInst)
406 outs << " [Instruction]";
407 if (diffRegs)
408 outs << " [IntRegs]";
409 if (diffTpc)
410 outs << " [Tpc]";
411 if (diffTnpc)
412 outs << " [Tnpc]";

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448
449 outs << right << setfill(' ') << setw(15)
450 << "M5 PC: " << "0x"<< setw(16) << setfill('0')
451 << hex << m5Pc << endl;
452 outs << setfill(' ') << setw(15)
453 << "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
454 << lgnPc << endl << endl;
455
456 outs << right << setfill(' ') << setw(15)
457 << "M5 CC: " << "0x"<< setw(16) << setfill('0')
458 << hex << thread->getCpuPtr()->instCount() << endl;
459 outs << setfill(' ') << setw(15)
460 << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
461 << shared_data->cycle_count << endl << endl;
462
463 outs << setfill(' ') << setw(15)
464 << "M5 Inst: " << "0x"<< setw(8)
465 << setfill('0') << hex << staticInst->machInst
466 << staticInst->disassemble(m5Pc, debugSymbolTable)
467 << endl;
468
469 StaticInstPtr legionInst =
470 StaticInst::decode(makeExtMI(shared_data->instruction,
471 thread));

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483 shared_data->hpstate | (1 << 11));
484 printRegPair(outs, "Htba",
485 thread->readMiscReg(MISCREG_HTBA),
486 shared_data->htba);
487 printRegPair(outs, "Pstate",
488 thread->readMiscReg(MISCREG_PSTATE),
489 shared_data->pstate);
490 printRegPair(outs, "Y",
490 //thread->readMiscReg(MISCREG_Y),
491 thread->readMiscReg(NumIntArchRegs + 1),
491 thread->readMiscReg(MISCREG_Y),
492 shared_data->y);
493 printRegPair(outs, "Ccr",
494 //thread->readMiscReg(MISCREG_CCR),
495 thread->readMiscReg(NumIntArchRegs + 2),
494 thread->readMiscReg(MISCREG_CCR),
495 shared_data->ccr);
496 printRegPair(outs, "Tl",
497 thread->readMiscReg(MISCREG_TL),
498 shared_data->tl);
499 printRegPair(outs, "Gl",
500 thread->readMiscReg(MISCREG_GL),
501 shared_data->gl);
502 printRegPair(outs, "Asi",
503 thread->readMiscReg(MISCREG_ASI),
504 shared_data->asi);
505 printRegPair(outs, "Pil",
506 thread->readMiscReg(MISCREG_PIL),
507 shared_data->pil);
508 printRegPair(outs, "Cwp",
509 thread->readMiscReg(MISCREG_CWP),
510 shared_data->cwp);
511 printRegPair(outs, "Cansave",
513 //thread->readMiscReg(MISCREG_CANSAVE),
514 thread->readIntReg(NumIntArchRegs + 3),
512 thread->readMiscReg(MISCREG_CANSAVE),
513 shared_data->cansave);
514 printRegPair(outs, "Canrestore",
517 //thread->readMiscReg(MISCREG_CANRESTORE),
518 thread->readIntReg(NumIntArchRegs + 4),
515 thread->readMiscReg(MISCREG_CANRESTORE),
516 shared_data->canrestore);
517 printRegPair(outs, "Otherwin",
521 //thread->readMiscReg(MISCREG_OTHERWIN),
522 thread->readIntReg(NumIntArchRegs + 5),
518 thread->readMiscReg(MISCREG_OTHERWIN),
519 shared_data->otherwin);
520 printRegPair(outs, "Cleanwin",
525 //thread->readMiscReg(MISCREG_CLEANWIN),
526 thread->readIntReg(NumIntArchRegs + 6),
521 thread->readMiscReg(MISCREG_CLEANWIN),
522 shared_data->cleanwin);
523 outs << endl;
524 for (int i = 1; i <= MaxTL; i++) {
525 printLevelHeader(outs, i);
526 printColumnLabels(outs);
527 thread->setMiscReg(MISCREG_TL, i);
528 printRegPair(outs, "Tpc",
529 thread->readMiscReg(MISCREG_TPC),

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