1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Lisa Hsu 30 * Nathan Binkert 31 * Steve Raasch 32 */ 33 34#include <iomanip> 35 36#include "arch/isa_traits.hh" 37#include "arch/utility.hh" 38#include "base/loader/symtab.hh" 39#include "cpu/base.hh" 40#include "cpu/exetrace.hh" 41#include "cpu/static_inst.hh" 42#include "cpu/thread_context.hh" 43#include "config/the_isa.hh" 44#include "enums/OpClass.hh" 45 46using namespace std; 47using namespace TheISA; 48 49namespace Trace { 50 51void 52ExeTracerRecord::dumpTicks(ostream &outs) 53{ 54 ccprintf(outs, "%7d: ", when); 55} 56 57void 58Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) 59{ 60 ostream &outs = Trace::output(); 61 62 if (IsOn(ExecTicks)) 63 dumpTicks(outs); 64 65 outs << thread->getCpuPtr()->name() << " "; 66 67 if (IsOn(ExecSpeculative)) 68 outs << (misspeculating ? "-" : "+") << " "; 69 70 if (IsOn(ExecThread)) 71 outs << "T" << thread->threadId() << " : "; 72 73 std::string sym_str; 74 Addr sym_addr;
| 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Lisa Hsu 30 * Nathan Binkert 31 * Steve Raasch 32 */ 33 34#include <iomanip> 35 36#include "arch/isa_traits.hh" 37#include "arch/utility.hh" 38#include "base/loader/symtab.hh" 39#include "cpu/base.hh" 40#include "cpu/exetrace.hh" 41#include "cpu/static_inst.hh" 42#include "cpu/thread_context.hh" 43#include "config/the_isa.hh" 44#include "enums/OpClass.hh" 45 46using namespace std; 47using namespace TheISA; 48 49namespace Trace { 50 51void 52ExeTracerRecord::dumpTicks(ostream &outs) 53{ 54 ccprintf(outs, "%7d: ", when); 55} 56 57void 58Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran) 59{ 60 ostream &outs = Trace::output(); 61 62 if (IsOn(ExecTicks)) 63 dumpTicks(outs); 64 65 outs << thread->getCpuPtr()->name() << " "; 66 67 if (IsOn(ExecSpeculative)) 68 outs << (misspeculating ? "-" : "+") << " "; 69 70 if (IsOn(ExecThread)) 71 outs << "T" << thread->threadId() << " : "; 72 73 std::string sym_str; 74 Addr sym_addr;
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75 Addr cur_pc = PC; 76#if THE_ISA == ARM_ISA 77 cur_pc &= ~PcModeMask; 78#endif
| 75 Addr cur_pc = pc.instAddr();
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79 if (debugSymbolTable 80 && IsOn(ExecSymbol) 81#if FULL_SYSTEM 82 && !inUserMode(thread) 83#endif 84 && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { 85 if (cur_pc != sym_addr) 86 sym_str += csprintf("+%d",cur_pc - sym_addr); 87 outs << "@" << sym_str;
| 76 if (debugSymbolTable 77 && IsOn(ExecSymbol) 78#if FULL_SYSTEM 79 && !inUserMode(thread) 80#endif 81 && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { 82 if (cur_pc != sym_addr) 83 sym_str += csprintf("+%d",cur_pc - sym_addr); 84 outs << "@" << sym_str;
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88 } 89 else {
| 85 } else {
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90 outs << "0x" << hex << cur_pc; 91 } 92 93 if (inst->isMicroop()) {
| 86 outs << "0x" << hex << cur_pc; 87 } 88 89 if (inst->isMicroop()) {
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94 outs << "." << setw(2) << dec << upc;
| 90 outs << "." << setw(2) << dec << pc.microPC();
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95 } else { 96 outs << " "; 97 } 98 99 outs << " : "; 100 101 // 102 // Print decoded instruction 103 // 104 105 outs << setw(26) << left; 106 outs << inst->disassemble(cur_pc, debugSymbolTable); 107 108 if (ran) { 109 outs << " : "; 110 111 if (IsOn(ExecOpClass)) { 112 outs << Enums::OpClassStrings[inst->opClass()] << " : "; 113 } 114 115 if (IsOn(ExecResult) && predicate == false) { 116 outs << "Predicated False"; 117 } 118 119 if (IsOn(ExecResult) && data_status != DataInvalid) { 120 ccprintf(outs, " D=%#018x", data.as_int); 121 } 122 123 if (IsOn(ExecEffAddr) && addr_valid) 124 outs << " A=0x" << hex << addr; 125 126 if (IsOn(ExecFetchSeq) && fetch_seq_valid) 127 outs << " FetchSeq=" << dec << fetch_seq; 128 129 if (IsOn(ExecCPSeq) && cp_seq_valid) 130 outs << " CPSeq=" << dec << cp_seq; 131 } 132 133 // 134 // End of line... 135 // 136 outs << endl; 137} 138 139void 140Trace::ExeTracerRecord::dump() 141{ 142 /* 143 * The behavior this check tries to achieve is that if ExecMacro is on, 144 * the macroop will be printed. If it's on and microops are also on, it's 145 * printed before the microops start printing to give context. If the 146 * microops aren't printed, then it's printed only when the final microop 147 * finishes. Macroops then behave like regular instructions and don't 148 * complete/print when they fault. 149 */ 150 if (IsOn(ExecMacro) && staticInst->isMicroop() && 151 ((IsOn(ExecMicro) && 152 macroStaticInst && staticInst->isFirstMicroop()) || 153 (!IsOn(ExecMicro) && 154 macroStaticInst && staticInst->isLastMicroop()))) { 155 traceInst(macroStaticInst, false); 156 } 157 if (IsOn(ExecMicro) || !staticInst->isMicroop()) { 158 traceInst(staticInst, true); 159 } 160} 161 162/* namespace Trace */ } 163 164//////////////////////////////////////////////////////////////////////// 165// 166// ExeTracer Simulation Object 167// 168Trace::ExeTracer * 169ExeTracerParams::create() 170{ 171 return new Trace::ExeTracer(this); 172};
| 91 } else { 92 outs << " "; 93 } 94 95 outs << " : "; 96 97 // 98 // Print decoded instruction 99 // 100 101 outs << setw(26) << left; 102 outs << inst->disassemble(cur_pc, debugSymbolTable); 103 104 if (ran) { 105 outs << " : "; 106 107 if (IsOn(ExecOpClass)) { 108 outs << Enums::OpClassStrings[inst->opClass()] << " : "; 109 } 110 111 if (IsOn(ExecResult) && predicate == false) { 112 outs << "Predicated False"; 113 } 114 115 if (IsOn(ExecResult) && data_status != DataInvalid) { 116 ccprintf(outs, " D=%#018x", data.as_int); 117 } 118 119 if (IsOn(ExecEffAddr) && addr_valid) 120 outs << " A=0x" << hex << addr; 121 122 if (IsOn(ExecFetchSeq) && fetch_seq_valid) 123 outs << " FetchSeq=" << dec << fetch_seq; 124 125 if (IsOn(ExecCPSeq) && cp_seq_valid) 126 outs << " CPSeq=" << dec << cp_seq; 127 } 128 129 // 130 // End of line... 131 // 132 outs << endl; 133} 134 135void 136Trace::ExeTracerRecord::dump() 137{ 138 /* 139 * The behavior this check tries to achieve is that if ExecMacro is on, 140 * the macroop will be printed. If it's on and microops are also on, it's 141 * printed before the microops start printing to give context. If the 142 * microops aren't printed, then it's printed only when the final microop 143 * finishes. Macroops then behave like regular instructions and don't 144 * complete/print when they fault. 145 */ 146 if (IsOn(ExecMacro) && staticInst->isMicroop() && 147 ((IsOn(ExecMicro) && 148 macroStaticInst && staticInst->isFirstMicroop()) || 149 (!IsOn(ExecMicro) && 150 macroStaticInst && staticInst->isLastMicroop()))) { 151 traceInst(macroStaticInst, false); 152 } 153 if (IsOn(ExecMicro) || !staticInst->isMicroop()) { 154 traceInst(staticInst, true); 155 } 156} 157 158/* namespace Trace */ } 159 160//////////////////////////////////////////////////////////////////////// 161// 162// ExeTracer Simulation Object 163// 164Trace::ExeTracer * 165ExeTracerParams::create() 166{ 167 return new Trace::ExeTracer(this); 168};
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