1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <iomanip>
35
36#include "arch/isa_traits.hh"
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <iomanip>
35
36#include "arch/isa_traits.hh"
|
37#include "base/loader/symtab.hh"
38#include "cpu/base.hh"
39#include "cpu/exetrace.hh"
40#include "cpu/static_inst.hh"
41#include "cpu/thread_context.hh"
42#include "config/the_isa.hh"
43#include "enums/OpClass.hh"
44
45using namespace std;
46using namespace TheISA;
47
48namespace Trace {
49
50void
51ExeTracerRecord::dumpTicks(ostream &outs)
52{
53 ccprintf(outs, "%7d: ", when);
54}
55
56void
57Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
58{
59 ostream &outs = Trace::output();
60
61 if (IsOn(ExecTicks))
62 dumpTicks(outs);
63
64 outs << thread->getCpuPtr()->name() << " ";
65
66 if (IsOn(ExecSpeculative))
67 outs << (misspeculating ? "-" : "+") << " ";
68
69 if (IsOn(ExecThread))
70 outs << "T" << thread->threadId() << " : ";
71
72 std::string sym_str;
73 Addr sym_addr;
74 Addr cur_pc = PC;
75#if THE_ISA == ARM_ISA
76 cur_pc &= ~PcModeMask;
77#endif
78 if (debugSymbolTable
79 && IsOn(ExecSymbol)
80#if FULL_SYSTEM
81 && !inUserMode(thread)
82#endif
83 && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
84 if (cur_pc != sym_addr)
85 sym_str += csprintf("+%d",cur_pc - sym_addr);
86 outs << "@" << sym_str;
87 }
88 else {
89 outs << "0x" << hex << cur_pc;
90 }
91
92 if (inst->isMicroop()) {
93 outs << "." << setw(2) << dec << upc;
94 } else {
95 outs << " ";
96 }
97
98 outs << " : ";
99
100 //
101 // Print decoded instruction
102 //
103
104 outs << setw(26) << left;
105 outs << inst->disassemble(cur_pc, debugSymbolTable);
106
107 if (ran) {
108 outs << " : ";
109
110 if (IsOn(ExecOpClass)) {
111 outs << Enums::OpClassStrings[inst->opClass()] << " : ";
112 }
113
114 if (IsOn(ExecResult) && predicate == false) {
115 outs << "Predicated False";
116 }
117
118 if (IsOn(ExecResult) && data_status != DataInvalid) {
119 ccprintf(outs, " D=%#018x", data.as_int);
120 }
121
122 if (IsOn(ExecEffAddr) && addr_valid)
123 outs << " A=0x" << hex << addr;
124
125 if (IsOn(ExecFetchSeq) && fetch_seq_valid)
126 outs << " FetchSeq=" << dec << fetch_seq;
127
128 if (IsOn(ExecCPSeq) && cp_seq_valid)
129 outs << " CPSeq=" << dec << cp_seq;
130 }
131
132 //
133 // End of line...
134 //
135 outs << endl;
136}
137
138void
139Trace::ExeTracerRecord::dump()
140{
141 /*
142 * The behavior this check tries to achieve is that if ExecMacro is on,
143 * the macroop will be printed. If it's on and microops are also on, it's
144 * printed before the microops start printing to give context. If the
145 * microops aren't printed, then it's printed only when the final microop
146 * finishes. Macroops then behave like regular instructions and don't
147 * complete/print when they fault.
148 */
149 if (IsOn(ExecMacro) && staticInst->isMicroop() &&
150 ((IsOn(ExecMicro) &&
151 macroStaticInst && staticInst->isFirstMicroop()) ||
152 (!IsOn(ExecMicro) &&
153 macroStaticInst && staticInst->isLastMicroop()))) {
154 traceInst(macroStaticInst, false);
155 }
156 if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
157 traceInst(staticInst, true);
158 }
159}
160
161/* namespace Trace */ }
162
163////////////////////////////////////////////////////////////////////////
164//
165// ExeTracer Simulation Object
166//
167Trace::ExeTracer *
168ExeTracerParams::create()
169{
170 return new Trace::ExeTracer(this);
171};
| 38#include "base/loader/symtab.hh"
39#include "cpu/base.hh"
40#include "cpu/exetrace.hh"
41#include "cpu/static_inst.hh"
42#include "cpu/thread_context.hh"
43#include "config/the_isa.hh"
44#include "enums/OpClass.hh"
45
46using namespace std;
47using namespace TheISA;
48
49namespace Trace {
50
51void
52ExeTracerRecord::dumpTicks(ostream &outs)
53{
54 ccprintf(outs, "%7d: ", when);
55}
56
57void
58Trace::ExeTracerRecord::traceInst(StaticInstPtr inst, bool ran)
59{
60 ostream &outs = Trace::output();
61
62 if (IsOn(ExecTicks))
63 dumpTicks(outs);
64
65 outs << thread->getCpuPtr()->name() << " ";
66
67 if (IsOn(ExecSpeculative))
68 outs << (misspeculating ? "-" : "+") << " ";
69
70 if (IsOn(ExecThread))
71 outs << "T" << thread->threadId() << " : ";
72
73 std::string sym_str;
74 Addr sym_addr;
75 Addr cur_pc = PC;
76#if THE_ISA == ARM_ISA
77 cur_pc &= ~PcModeMask;
78#endif
79 if (debugSymbolTable
80 && IsOn(ExecSymbol)
81#if FULL_SYSTEM
82 && !inUserMode(thread)
83#endif
84 && debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) {
85 if (cur_pc != sym_addr)
86 sym_str += csprintf("+%d",cur_pc - sym_addr);
87 outs << "@" << sym_str;
88 }
89 else {
90 outs << "0x" << hex << cur_pc;
91 }
92
93 if (inst->isMicroop()) {
94 outs << "." << setw(2) << dec << upc;
95 } else {
96 outs << " ";
97 }
98
99 outs << " : ";
100
101 //
102 // Print decoded instruction
103 //
104
105 outs << setw(26) << left;
106 outs << inst->disassemble(cur_pc, debugSymbolTable);
107
108 if (ran) {
109 outs << " : ";
110
111 if (IsOn(ExecOpClass)) {
112 outs << Enums::OpClassStrings[inst->opClass()] << " : ";
113 }
114
115 if (IsOn(ExecResult) && predicate == false) {
116 outs << "Predicated False";
117 }
118
119 if (IsOn(ExecResult) && data_status != DataInvalid) {
120 ccprintf(outs, " D=%#018x", data.as_int);
121 }
122
123 if (IsOn(ExecEffAddr) && addr_valid)
124 outs << " A=0x" << hex << addr;
125
126 if (IsOn(ExecFetchSeq) && fetch_seq_valid)
127 outs << " FetchSeq=" << dec << fetch_seq;
128
129 if (IsOn(ExecCPSeq) && cp_seq_valid)
130 outs << " CPSeq=" << dec << cp_seq;
131 }
132
133 //
134 // End of line...
135 //
136 outs << endl;
137}
138
139void
140Trace::ExeTracerRecord::dump()
141{
142 /*
143 * The behavior this check tries to achieve is that if ExecMacro is on,
144 * the macroop will be printed. If it's on and microops are also on, it's
145 * printed before the microops start printing to give context. If the
146 * microops aren't printed, then it's printed only when the final microop
147 * finishes. Macroops then behave like regular instructions and don't
148 * complete/print when they fault.
149 */
150 if (IsOn(ExecMacro) && staticInst->isMicroop() &&
151 ((IsOn(ExecMicro) &&
152 macroStaticInst && staticInst->isFirstMicroop()) ||
153 (!IsOn(ExecMicro) &&
154 macroStaticInst && staticInst->isLastMicroop()))) {
155 traceInst(macroStaticInst, false);
156 }
157 if (IsOn(ExecMicro) || !staticInst->isMicroop()) {
158 traceInst(staticInst, true);
159 }
160}
161
162/* namespace Trace */ }
163
164////////////////////////////////////////////////////////////////////////
165//
166// ExeTracer Simulation Object
167//
168Trace::ExeTracer *
169ExeTracerParams::create()
170{
171 return new Trace::ExeTracer(this);
172};
|