1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36
37#include "arch/regfile.hh"
38#include "base/loader/symtab.hh"
39#include "cpu/base.hh"
40#include "cpu/exetrace.hh"
41#include "cpu/static_inst.hh"
42#include "sim/param.hh"
43#include "sim/system.hh"
44
45//XXX This is temporary
46#include "arch/isa_specific.hh"
47
48using namespace std;
49using namespace TheISA;
50
51////////////////////////////////////////////////////////////////////////
52//
53// Methods for the InstRecord object
54//
55
56
57void
58Trace::InstRecord::dump(ostream &outs)
59{
60 if (flags[PRINT_REG_DELTA])
61 {
62#if THE_ISA == SPARC_ISA
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36
37#include "arch/regfile.hh"
38#include "base/loader/symtab.hh"
39#include "cpu/base.hh"
40#include "cpu/exetrace.hh"
41#include "cpu/static_inst.hh"
42#include "sim/param.hh"
43#include "sim/system.hh"
44
45//XXX This is temporary
46#include "arch/isa_specific.hh"
47
48using namespace std;
49using namespace TheISA;
50
51////////////////////////////////////////////////////////////////////////
52//
53// Methods for the InstRecord object
54//
55
56
57void
58Trace::InstRecord::dump(ostream &outs)
59{
60 if (flags[PRINT_REG_DELTA])
61 {
62#if THE_ISA == SPARC_ISA
|
63 static uint64_t regs[32] = {
64 0, 0, 0, 0, 0, 0, 0, 0,
65 0, 0, 0, 0, 0, 0, 0, 0,
66 0, 0, 0, 0, 0, 0, 0, 0,
67 0, 0, 0, 0, 0, 0, 0, 0};
68 static uint64_t ccr = 0;
69 static uint64_t y = 0;
70 static uint64_t floats[32];
71 uint64_t newVal;
72 static const char * prefixes[4] = {"G", "O", "L", "I"};
73
74 char buf[256];
75 sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
76 outs << buf;
77 sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
78 outs << buf;
79 newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
80 if(newVal != ccr)
| 63 //Don't print what happens for each micro-op, just print out
64 //once at the last op, and for regular instructions.
65 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
|
81 {
| 66 {
|
82 sprintf(buf, " CCR = 0x%016llx", newVal);
| 67 static uint64_t regs[32] = {
68 0, 0, 0, 0, 0, 0, 0, 0,
69 0, 0, 0, 0, 0, 0, 0, 0,
70 0, 0, 0, 0, 0, 0, 0, 0,
71 0, 0, 0, 0, 0, 0, 0, 0};
72 static uint64_t ccr = 0;
73 static uint64_t y = 0;
74 static uint64_t floats[32];
75 uint64_t newVal;
76 static const char * prefixes[4] = {"G", "O", "L", "I"};
77
78 char buf[256];
79 sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
|
83 outs << buf;
| 80 outs << buf;
|
84 ccr = newVal;
85 }
86 newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
87 if(newVal != y)
88 {
89 sprintf(buf, " Y = 0x%016llx", newVal);
| 81 sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
|
90 outs << buf;
| 82 outs << buf;
|
91 y = newVal;
92 }
93 for(int y = 0; y < 4; y++)
94 {
95 for(int x = 0; x < 8; x++)
| 83 newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
84 if(newVal != ccr)
|
96 {
| 85 {
|
97 int index = x + 8 * y;
98 newVal = thread->readIntReg(index);
99 if(regs[index] != newVal)
| 86 sprintf(buf, " CCR = 0x%016llx", newVal);
87 outs << buf;
88 ccr = newVal;
89 }
90 newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
91 if(newVal != y)
92 {
93 sprintf(buf, " Y = 0x%016llx", newVal);
94 outs << buf;
95 y = newVal;
96 }
97 for(int y = 0; y < 4; y++)
98 {
99 for(int x = 0; x < 8; x++)
|
100 {
| 100 {
|
101 sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
102 outs << buf;
103 regs[index] = newVal;
| 101 int index = x + 8 * y;
102 newVal = thread->readIntReg(index);
103 if(regs[index] != newVal)
104 {
105 sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
106 outs << buf;
107 regs[index] = newVal;
108 }
|
104 }
105 }
| 109 }
110 }
|
106 }
107 for(int y = 0; y < 32; y++)
108 {
109 newVal = thread->readFloatRegBits(2 * y, 64);
110 if(floats[y] != newVal)
| 111 for(int y = 0; y < 32; y++)
|
111 {
| 112 {
|
112 sprintf(buf, " F%d = 0x%016llx", y, newVal);
113 outs << buf;
114 floats[y] = newVal;
| 113 newVal = thread->readFloatRegBits(2 * y, 64);
114 if(floats[y] != newVal)
115 {
116 sprintf(buf, " F%d = 0x%016llx", 2 * y, newVal);
117 outs << buf;
118 floats[y] = newVal;
119 }
|
115 }
| 120 }
|
| 121 outs << endl;
|
116 }
| 122 }
|
117 outs << endl;
| |
118#endif
119 }
120 else if (flags[INTEL_FORMAT]) {
121#if FULL_SYSTEM
122 bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
123#else
124 bool is_trace_system = true;
125#endif
126 if (is_trace_system) {
127 ccprintf(outs, "%7d ) ", cycle);
128 outs << "0x" << hex << PC << ":\t";
129 if (staticInst->isLoad()) {
130 outs << "<RD 0x" << hex << addr;
131 outs << ">";
132 } else if (staticInst->isStore()) {
133 outs << "<WR 0x" << hex << addr;
134 outs << ">";
135 }
136 outs << endl;
137 }
138 } else {
139 if (flags[PRINT_CYCLE])
140 ccprintf(outs, "%7d: ", cycle);
141
142 outs << thread->getCpuPtr()->name() << " ";
143
144 if (flags[TRACE_MISSPEC])
145 outs << (misspeculating ? "-" : "+") << " ";
146
147 if (flags[PRINT_THREAD_NUM])
148 outs << "T" << thread->getThreadNum() << " : ";
149
150
151 std::string sym_str;
152 Addr sym_addr;
153 if (debugSymbolTable
154 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
155 && flags[PC_SYMBOL]) {
156 if (PC != sym_addr)
157 sym_str += csprintf("+%d", PC - sym_addr);
158 outs << "@" << sym_str << " : ";
159 }
160 else {
161 outs << "0x" << hex << PC << " : ";
162 }
163
164 //
165 // Print decoded instruction
166 //
167
168#if defined(__GNUC__) && (__GNUC__ < 3)
169 // There's a bug in gcc 2.x library that prevents setw()
170 // from working properly on strings
171 string mc(staticInst->disassemble(PC, debugSymbolTable));
172 while (mc.length() < 26)
173 mc += " ";
174 outs << mc;
175#else
176 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
177#endif
178
179 outs << " : ";
180
181 if (flags[PRINT_OP_CLASS]) {
182 outs << opClassStrings[staticInst->opClass()] << " : ";
183 }
184
185 if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
186 outs << " D=";
187#if 0
188 if (data_status == DataDouble)
189 ccprintf(outs, "%f", data.as_double);
190 else
191 ccprintf(outs, "%#018x", data.as_int);
192#else
193 ccprintf(outs, "%#018x", data.as_int);
194#endif
195 }
196
197 if (flags[PRINT_EFF_ADDR] && addr_valid)
198 outs << " A=0x" << hex << addr;
199
200 if (flags[PRINT_INT_REGS] && regs_valid) {
201 for (int i = 0; i < TheISA::NumIntRegs;)
202 for (int j = i + 1; i <= j; i++)
203 ccprintf(outs, "r%02d = %#018x%s", i,
204 iregs->regs.readReg(i),
205 ((i == j) ? "\n" : " "));
206 outs << "\n";
207 }
208
209 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
210 outs << " FetchSeq=" << dec << fetch_seq;
211
212 if (flags[PRINT_CP_SEQ] && cp_seq_valid)
213 outs << " CPSeq=" << dec << cp_seq;
214
215 //
216 // End of line...
217 //
218 outs << endl;
219 }
220}
221
222
223vector<bool> Trace::InstRecord::flags(NUM_BITS);
224string Trace::InstRecord::trace_system;
225
226////////////////////////////////////////////////////////////////////////
227//
228// Parameter space for per-cycle execution address tracing options.
229// Derive from ParamContext so we can override checkParams() function.
230//
231class ExecutionTraceParamContext : public ParamContext
232{
233 public:
234 ExecutionTraceParamContext(const string &_iniSection)
235 : ParamContext(_iniSection)
236 {
237 }
238
239 void checkParams(); // defined at bottom of file
240};
241
242ExecutionTraceParamContext exeTraceParams("exetrace");
243
244Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
245 "capture speculative instructions", true);
246
247Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
248 "print cycle number", true);
249Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
250 "print op class", true);
251Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
252 "print thread number", true);
253Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
254 "print effective address", true);
255Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
256 "print result data", true);
257Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
258 "print all integer regs", false);
259Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
260 "print fetch sequence number", false);
261Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
262 "print correct-path sequence number", false);
263Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
264 "print which registers changed to what", false);
265Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
266 "Use symbols for the PC if available", true);
267Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
268 "print trace in intel compatible format", false);
269Param<string> exe_trace_system(&exeTraceParams, "trace_system",
270 "print trace of which system (client or server)",
271 "client");
272
273
274//
275// Helper function for ExecutionTraceParamContext::checkParams() just
276// to get us into the InstRecord namespace
277//
278void
279Trace::InstRecord::setParams()
280{
281 flags[TRACE_MISSPEC] = exe_trace_spec;
282
283 flags[PRINT_CYCLE] = exe_trace_print_cycle;
284 flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
285 flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
286 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
287 flags[PRINT_EFF_ADDR] = exe_trace_print_data;
288 flags[PRINT_INT_REGS] = exe_trace_print_iregs;
289 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
290 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
291 flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
292 flags[PC_SYMBOL] = exe_trace_pc_symbol;
293 flags[INTEL_FORMAT] = exe_trace_intel_format;
294 trace_system = exe_trace_system;
295}
296
297void
298ExecutionTraceParamContext::checkParams()
299{
300 Trace::InstRecord::setParams();
301}
302
| 123#endif
124 }
125 else if (flags[INTEL_FORMAT]) {
126#if FULL_SYSTEM
127 bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
128#else
129 bool is_trace_system = true;
130#endif
131 if (is_trace_system) {
132 ccprintf(outs, "%7d ) ", cycle);
133 outs << "0x" << hex << PC << ":\t";
134 if (staticInst->isLoad()) {
135 outs << "<RD 0x" << hex << addr;
136 outs << ">";
137 } else if (staticInst->isStore()) {
138 outs << "<WR 0x" << hex << addr;
139 outs << ">";
140 }
141 outs << endl;
142 }
143 } else {
144 if (flags[PRINT_CYCLE])
145 ccprintf(outs, "%7d: ", cycle);
146
147 outs << thread->getCpuPtr()->name() << " ";
148
149 if (flags[TRACE_MISSPEC])
150 outs << (misspeculating ? "-" : "+") << " ";
151
152 if (flags[PRINT_THREAD_NUM])
153 outs << "T" << thread->getThreadNum() << " : ";
154
155
156 std::string sym_str;
157 Addr sym_addr;
158 if (debugSymbolTable
159 && debugSymbolTable->findNearestSymbol(PC, sym_str, sym_addr)
160 && flags[PC_SYMBOL]) {
161 if (PC != sym_addr)
162 sym_str += csprintf("+%d", PC - sym_addr);
163 outs << "@" << sym_str << " : ";
164 }
165 else {
166 outs << "0x" << hex << PC << " : ";
167 }
168
169 //
170 // Print decoded instruction
171 //
172
173#if defined(__GNUC__) && (__GNUC__ < 3)
174 // There's a bug in gcc 2.x library that prevents setw()
175 // from working properly on strings
176 string mc(staticInst->disassemble(PC, debugSymbolTable));
177 while (mc.length() < 26)
178 mc += " ";
179 outs << mc;
180#else
181 outs << setw(26) << left << staticInst->disassemble(PC, debugSymbolTable);
182#endif
183
184 outs << " : ";
185
186 if (flags[PRINT_OP_CLASS]) {
187 outs << opClassStrings[staticInst->opClass()] << " : ";
188 }
189
190 if (flags[PRINT_RESULT_DATA] && data_status != DataInvalid) {
191 outs << " D=";
192#if 0
193 if (data_status == DataDouble)
194 ccprintf(outs, "%f", data.as_double);
195 else
196 ccprintf(outs, "%#018x", data.as_int);
197#else
198 ccprintf(outs, "%#018x", data.as_int);
199#endif
200 }
201
202 if (flags[PRINT_EFF_ADDR] && addr_valid)
203 outs << " A=0x" << hex << addr;
204
205 if (flags[PRINT_INT_REGS] && regs_valid) {
206 for (int i = 0; i < TheISA::NumIntRegs;)
207 for (int j = i + 1; i <= j; i++)
208 ccprintf(outs, "r%02d = %#018x%s", i,
209 iregs->regs.readReg(i),
210 ((i == j) ? "\n" : " "));
211 outs << "\n";
212 }
213
214 if (flags[PRINT_FETCH_SEQ] && fetch_seq_valid)
215 outs << " FetchSeq=" << dec << fetch_seq;
216
217 if (flags[PRINT_CP_SEQ] && cp_seq_valid)
218 outs << " CPSeq=" << dec << cp_seq;
219
220 //
221 // End of line...
222 //
223 outs << endl;
224 }
225}
226
227
228vector<bool> Trace::InstRecord::flags(NUM_BITS);
229string Trace::InstRecord::trace_system;
230
231////////////////////////////////////////////////////////////////////////
232//
233// Parameter space for per-cycle execution address tracing options.
234// Derive from ParamContext so we can override checkParams() function.
235//
236class ExecutionTraceParamContext : public ParamContext
237{
238 public:
239 ExecutionTraceParamContext(const string &_iniSection)
240 : ParamContext(_iniSection)
241 {
242 }
243
244 void checkParams(); // defined at bottom of file
245};
246
247ExecutionTraceParamContext exeTraceParams("exetrace");
248
249Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
250 "capture speculative instructions", true);
251
252Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
253 "print cycle number", true);
254Param<bool> exe_trace_print_opclass(&exeTraceParams, "print_opclass",
255 "print op class", true);
256Param<bool> exe_trace_print_thread(&exeTraceParams, "print_thread",
257 "print thread number", true);
258Param<bool> exe_trace_print_effaddr(&exeTraceParams, "print_effaddr",
259 "print effective address", true);
260Param<bool> exe_trace_print_data(&exeTraceParams, "print_data",
261 "print result data", true);
262Param<bool> exe_trace_print_iregs(&exeTraceParams, "print_iregs",
263 "print all integer regs", false);
264Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
265 "print fetch sequence number", false);
266Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
267 "print correct-path sequence number", false);
268Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
269 "print which registers changed to what", false);
270Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
271 "Use symbols for the PC if available", true);
272Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
273 "print trace in intel compatible format", false);
274Param<string> exe_trace_system(&exeTraceParams, "trace_system",
275 "print trace of which system (client or server)",
276 "client");
277
278
279//
280// Helper function for ExecutionTraceParamContext::checkParams() just
281// to get us into the InstRecord namespace
282//
283void
284Trace::InstRecord::setParams()
285{
286 flags[TRACE_MISSPEC] = exe_trace_spec;
287
288 flags[PRINT_CYCLE] = exe_trace_print_cycle;
289 flags[PRINT_OP_CLASS] = exe_trace_print_opclass;
290 flags[PRINT_THREAD_NUM] = exe_trace_print_thread;
291 flags[PRINT_RESULT_DATA] = exe_trace_print_effaddr;
292 flags[PRINT_EFF_ADDR] = exe_trace_print_data;
293 flags[PRINT_INT_REGS] = exe_trace_print_iregs;
294 flags[PRINT_FETCH_SEQ] = exe_trace_print_fetchseq;
295 flags[PRINT_CP_SEQ] = exe_trace_print_cp_seq;
296 flags[PRINT_REG_DELTA] = exe_trace_print_reg_delta;
297 flags[PC_SYMBOL] = exe_trace_pc_symbol;
298 flags[INTEL_FORMAT] = exe_trace_intel_format;
299 trace_system = exe_trace_system;
300}
301
302void
303ExecutionTraceParamContext::checkParams()
304{
305 Trace::InstRecord::setParams();
306}
307
|