1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Lisa Hsu
30 * Nathan Binkert
31 * Steve Raasch
32 */
33
34#include <fstream>
35#include <iomanip>
36#include <sys/ipc.h>
37#include <sys/shm.h>
38
39#include "arch/regfile.hh"
40#include "arch/utility.hh"
41#include "base/loader/symtab.hh"
42#include "config/full_system.hh"
43#include "cpu/base.hh"
44#include "cpu/exetrace.hh"
45#include "cpu/static_inst.hh"
46#include "sim/param.hh"
47#include "sim/system.hh"
48
49#if FULL_SYSTEM

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59
60#if THE_ISA == SPARC_ISA && FULL_SYSTEM
61static int diffcount = 0;
62static bool wasMicro = false;
63#endif
64
65namespace Trace {
66SharedData *shared_data = NULL;
67
68void
69setupSharedData()
70{
71 int shmfd = shmget('M' << 24 | getuid(), sizeof(SharedData), 0777);
72 if (shmfd < 0)
73 fatal("Couldn't get shared memory fd. Is Legion running?");
74

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144#endif
145
146void
147Trace::InstRecord::dump()
148{
149 ostream &outs = Trace::output();
150
151 DPRINTF(Sparc, "Instruction: %#X\n", staticInst->machInst);
152 if (IsOn(ExecRegDelta))
153 {
154#if THE_ISA == SPARC_ISA
155 //Don't print what happens for each micro-op, just print out
156 //once at the last op, and for regular instructions.
157 if(!staticInst->isMicroOp() || staticInst->isLastMicroOp())
158 {
159 static uint64_t regs[32] = {
160 0, 0, 0, 0, 0, 0, 0, 0,
161 0, 0, 0, 0, 0, 0, 0, 0,
162 0, 0, 0, 0, 0, 0, 0, 0,
163 0, 0, 0, 0, 0, 0, 0, 0};
164 static uint64_t ccr = 0;
165 static uint64_t y = 0;
166 static uint64_t floats[32];

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205 outs << " F" << dec << (2 * y) << " = " << hex << newVal;
206 floats[y] = newVal;
207 }
208 }
209 outs << dec << endl;
210 }
211#endif
212 }
213 else if (IsOn(ExecIntel)) {
214 ccprintf(outs, "%7d ) ", when);
215 outs << "0x" << hex << PC << ":\t";
216 if (staticInst->isLoad()) {
217 ccprintf(outs, "<RD %#x>", addr);
218 } else if (staticInst->isStore()) {
219 ccprintf(outs, "<WR %#x>", addr);
220 }
221 outs << endl;

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