1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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353 if (shared_data->cycle_count !=
354 thread->getCpuPtr()->instCount())
355 diffCC = true;
356
357 if (shared_data->instruction !=
358 (SparcISA::MachInst)staticInst->machInst) {
359 diffInst = true;
360 }
361 // assume we have %g0 working correctly
362 for (int i = 1; i < TheISA::NumIntArchRegs; i++) {
363 if (thread->readIntReg(i) != shared_data->intregs[i]) {
364 diffIntRegs = true;
365 }
366 }
367 for (int i = 0; i < TheISA::NumFloatRegs/2; i++) {
368 if (thread->readFloatRegBits(i*2,FloatRegFile::DoubleWidth) != shared_data->fpregs[i]) {
369 diffFpRegs = true;
370 }

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424 diffCwp = true;
425 //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
426 if(shared_data->cansave !=
427 thread->readIntReg(NumIntArchRegs + 3))
428 diffCansave = true;
429 //if(shared_data->canrestore !=
430 // thread->readMiscReg(MISCREG_CANRESTORE))
431 if(shared_data->canrestore !=
432 thread->readIntReg(NumIntArchRegs + 4))
433 diffCanrestore = true;
434 //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
435 if(shared_data->otherwin !=
436 thread->readIntReg(NumIntArchRegs + 6))
437 diffOtherwin = true;
438 //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
439 if(shared_data->cleanwin !=
440 thread->readIntReg(NumIntArchRegs + 5))
441 diffCleanwin = true;
442
443 for (int i = 0; i < 64; i++) {
444 if (shared_data->itb[i] != thread->getITBPtr()->TteRead(i))
445 diffTlb = true;
446 if (shared_data->dtb[i] != thread->getDTBPtr()->TteRead(i))
447 diffTlb = true;
448 }

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549 printRegPair(outs, "Htba",
550 thread->readMiscReg(MISCREG_HTBA),
551 shared_data->htba);
552 printRegPair(outs, "Pstate",
553 thread->readMiscReg(MISCREG_PSTATE),
554 shared_data->pstate);
555 printRegPair(outs, "Y",
556 //thread->readMiscReg(MISCREG_Y),
557 thread->readIntReg(NumIntArchRegs + 1),
558 shared_data->y);
559 printRegPair(outs, "Ccr",
560 //thread->readMiscReg(MISCREG_CCR),
561 thread->readIntReg(NumIntArchRegs + 2),
562 shared_data->ccr);
563 printRegPair(outs, "Tl",
564 thread->readMiscReg(MISCREG_TL),
565 shared_data->tl);
566 printRegPair(outs, "Gl",
567 thread->readMiscReg(MISCREG_GL),
568 shared_data->gl);
569 printRegPair(outs, "Asi",

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580 thread->readIntReg(NumIntArchRegs + 3),
581 shared_data->cansave);
582 printRegPair(outs, "Canrestore",
583 //thread->readMiscReg(MISCREG_CANRESTORE),
584 thread->readIntReg(NumIntArchRegs + 4),
585 shared_data->canrestore);
586 printRegPair(outs, "Otherwin",
587 //thread->readMiscReg(MISCREG_OTHERWIN),
588 thread->readIntReg(NumIntArchRegs + 6),
589 shared_data->otherwin);
590 printRegPair(outs, "Cleanwin",
591 //thread->readMiscReg(MISCREG_CLEANWIN),
592 thread->readIntReg(NumIntArchRegs + 5),
593 shared_data->cleanwin);
594 outs << endl;
595 for (int i = 1; i <= MaxTL; i++) {
596 printLevelHeader(outs, i);
597 printColumnLabels(outs);
598 thread->setMiscReg(MISCREG_TL, i);
599 printRegPair(outs, "Tpc",
600 thread->readMiscReg(MISCREG_TPC),

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