exec_context.hh (8779:2a590c51adb1) | exec_context.hh (10319:4207f9bfcceb) |
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1/* | 1/* |
2 * Copyright (c) 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
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2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright --- 11 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim | 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 11 unchanged lines hidden (view full) --- 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Kevin Lim |
41 * Andreas Sandberg |
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29 */ 30 | 42 */ 43 |
31#error "Cannot include this file" | 44#ifndef __CPU_EXEC_CONTEXT_HH__ 45#define __CPU_EXEC_CONTEXT_HH__ |
32 | 46 |
47#include "arch/registers.hh" 48#include "base/types.hh" 49#include "config/the_isa.hh" 50#include "cpu/static_inst_fwd.hh" 51#include "cpu/translation.hh" 52#include "sim/fault_fwd.hh" 53 |
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33/** | 54/** |
34 * The ExecContext is not a usable class. It is simply here for 35 * documentation purposes. It shows the interface that is used by the 36 * ISA to access and change CPU state. | 55 * The ExecContext is an abstract base class the provides the 56 * interface used by the ISA to manipulate the state of the CPU model. 57 * 58 * Register accessor methods in this class typically provide the index 59 * of the instruction's operand (e.g., 0 or 1), not the architectural 60 * register index, to simplify the implementation of register 61 * renaming. The architectural register index can be found by 62 * indexing into the instruction's own operand index table. 63 * 64 * @note The methods in this class typically take a raw pointer to the 65 * StaticInst is provided instead of a ref-counted StaticInstPtr to 66 * reduce overhead as an argument. This is fine as long as the 67 * implementation doesn't copy the pointer into any long-term storage 68 * (which is pretty hard to imagine they would have reason to do). |
37 */ 38class ExecContext { | 69 */ 70class ExecContext { |
39 // The register accessor methods provide the index of the 40 // instruction's operand (e.g., 0 or 1), not the architectural 41 // register index, to simplify the implementation of register 42 // renaming. We find the architectural register index by indexing 43 // into the instruction's own operand index table. Note that a 44 // raw pointer to the StaticInst is provided instead of a 45 // ref-counted StaticInstPtr to reduce overhead. This is fine as 46 // long as these methods don't copy the pointer into any long-term 47 // storage (which is pretty hard to imagine they would have reason 48 // to do). | 71 public: 72 typedef TheISA::IntReg IntReg; 73 typedef TheISA::PCState PCState; 74 typedef TheISA::FloatReg FloatReg; 75 typedef TheISA::FloatRegBits FloatRegBits; 76 typedef TheISA::MiscReg MiscReg; |
49 | 77 |
78 typedef TheISA::CCReg CCReg; 79 80 public: 81 /** 82 * @{ 83 * @name Integer Register Interfaces 84 * 85 */ 86 |
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50 /** Reads an integer register. */ | 87 /** Reads an integer register. */ |
51 uint64_t readIntRegOperand(const StaticInst *si, int idx); | 88 virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0; |
52 | 89 |
90 /** Sets an integer register to a value. */ 91 virtual void setIntRegOperand(const StaticInst *si, 92 int idx, IntReg val) = 0; 93 94 /** @} */ 95 96 97 /** 98 * @{ 99 * @name Floating Point Register Interfaces 100 */ 101 |
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53 /** Reads a floating point register of single register width. */ | 102 /** Reads a floating point register of single register width. */ |
54 FloatReg readFloatRegOperand(const StaticInst *si, int idx); | 103 virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0; |
55 56 /** Reads a floating point register in its binary format, instead 57 * of by value. */ | 104 105 /** Reads a floating point register in its binary format, instead 106 * of by value. */ |
58 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx); | 107 virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si, 108 int idx) = 0; |
59 | 109 |
60 /** Sets an integer register to a value. */ 61 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val); 62 | |
63 /** Sets a floating point register of single width to a value. */ | 110 /** Sets a floating point register of single width to a value. */ |
64 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val); | 111 virtual void setFloatRegOperand(const StaticInst *si, 112 int idx, FloatReg val) = 0; |
65 66 /** Sets the bits of a floating point register of single width 67 * to a binary value. */ | 113 114 /** Sets the bits of a floating point register of single width 115 * to a binary value. */ |
68 void setFloatRegOperandBits(const StaticInst *si, int idx, 69 FloatRegBits val); | 116 virtual void setFloatRegOperandBits(const StaticInst *si, 117 int idx, FloatRegBits val) = 0; |
70 | 118 |
71 /** Reads the PC. */ 72 uint64_t readPC(); 73 /** Reads the NextPC. */ 74 uint64_t readNextPC(); 75 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 76 uint64_t readNextNPC(); | 119 /** @} */ |
77 | 120 |
78 /** Sets the PC. */ 79 void setPC(uint64_t val); 80 /** Sets the NextPC. */ 81 void setNextPC(uint64_t val); 82 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 83 void setNextNPC(uint64_t val); | 121 /** 122 * @{ 123 * @name Condition Code Registers 124 */ 125 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 126 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 127 /** @} */ |
84 | 128 |
85 /** Reads a miscellaneous register. */ 86 MiscReg readMiscRegNoEffect(int misc_reg); | 129 /** 130 * @{ 131 * @name Misc Register Interfaces 132 */ 133 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0; 134 virtual void setMiscRegOperand(const StaticInst *si, 135 int idx, const MiscReg &val) = 0; |
87 | 136 |
88 /** Reads a miscellaneous register, handling any architectural 89 * side effects due to reading that register. */ 90 MiscReg readMiscReg(int misc_reg); | 137 /** 138 * Reads a miscellaneous register, handling any architectural 139 * side effects due to reading that register. 140 */ 141 virtual MiscReg readMiscReg(int misc_reg) = 0; |
91 | 142 |
92 /** Sets a miscellaneous register. */ 93 void setMiscRegNoEffect(int misc_reg, const MiscReg &val); | 143 /** 144 * Sets a miscellaneous register, handling any architectural 145 * side effects due to writing that register. 146 */ 147 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; |
94 | 148 |
95 /** Sets a miscellaneous register, handling any architectural 96 * side effects due to writing that register. */ 97 void setMiscReg(int misc_reg, const MiscReg &val); | 149 /** @} */ |
98 | 150 |
99 /** Records the effective address of the instruction. Only valid 100 * for memory ops. */ 101 void setEA(Addr EA); 102 /** Returns the effective address of the instruction. Only valid 103 * for memory ops. */ 104 Addr getEA(); | 151 /** 152 * @{ 153 * @name PC Control 154 */ 155 virtual PCState pcState() const = 0; 156 virtual void pcState(const PCState &val) = 0; 157 /** @} */ |
105 | 158 |
106 /** Returns a pointer to the ThreadContext. */ 107 ThreadContext *tcBase(); | 159 /** 160 * @{ 161 * @name Memory Interface 162 */ 163 /** 164 * Record the effective address of the instruction. 165 * 166 * @note Only valid for memory ops. 167 */ 168 virtual void setEA(Addr EA) = 0; 169 /** 170 * Get the effective address of the instruction. 171 * 172 * @note Only valid for memory ops. 173 */ 174 virtual Addr getEA() const = 0; |
108 | 175 |
109 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags); | 176 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, 177 unsigned int flags) = 0; |
110 | 178 |
111 Fault writeMem(uint8_t *data, unsigned size, 112 Addr addr, unsigned flags, uint64_t *res); | 179 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr, 180 unsigned int flags, uint64_t *res) = 0; |
113 | 181 |
114 /** Somewhat Alpha-specific function that handles returning from 115 * an error or interrupt. */ 116 Fault hwrei(); | 182 /** 183 * Sets the number of consecutive store conditional failures. 184 */ 185 virtual void setStCondFailures(unsigned int sc_failures) = 0; |
117 118 /** | 186 187 /** |
188 * Returns the number of consecutive store conditional failures. 189 */ 190 virtual unsigned int readStCondFailures() const = 0; 191 192 /** @} */ 193 194 /** 195 * @{ 196 * @name SysCall Emulation Interfaces 197 */ 198 199 /** 200 * Executes a syscall specified by the callnum. 201 */ 202 virtual void syscall(int64_t callnum) = 0; 203 204 /** @} */ 205 206 /** Returns a pointer to the ThreadContext. */ 207 virtual ThreadContext *tcBase() = 0; 208 209 /** 210 * @{ 211 * @name Alpha-Specific Interfaces 212 */ 213 214 /** 215 * Somewhat Alpha-specific function that handles returning from an 216 * error or interrupt. 217 */ 218 virtual Fault hwrei() = 0; 219 220 /** |
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119 * Check for special simulator handling of specific PAL calls. If 120 * return value is false, actual PAL call will be suppressed. 121 */ | 221 * Check for special simulator handling of specific PAL calls. If 222 * return value is false, actual PAL call will be suppressed. 223 */ |
122 bool simPalCheck(int palFunc); | 224 virtual bool simPalCheck(int palFunc) = 0; |
123 | 225 |
124 /** Executes a syscall specified by the callnum. */ 125 void syscall(int64_t callnum); | 226 /** @} */ |
126 | 227 |
127 /** Finish a DTB address translation. */ 128 void finishTranslation(WholeTranslationState *state); | 228 /** 229 * @{ 230 * @name ARM-Specific Interfaces 231 */ 232 233 virtual bool readPredicate() = 0; 234 virtual void setPredicate(bool val) = 0; 235 236 /** @} */ 237 238 /** 239 * @{ 240 * @name X86-Specific Interfaces 241 */ 242 243 /** 244 * Invalidate a page in the DTLB <i>and</i> ITLB. 245 */ 246 virtual void demapPage(Addr vaddr, uint64_t asn) = 0; 247 248 /** @} */ 249 250 /** 251 * @{ 252 * @name MIPS-Specific Interfaces 253 */ 254 255#if THE_ISA == MIPS_ISA 256 virtual MiscReg readRegOtherThread(int regIdx, 257 ThreadID tid = InvalidThreadID) = 0; 258 virtual void setRegOtherThread(int regIdx, MiscReg val, 259 ThreadID tid = InvalidThreadID) = 0; 260#endif 261 262 /** @} */ |
129}; | 263}; |
264 265#endif // __CPU_EXEC_CONTEXT_HH__ |
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