exec_context.hh (2665:a124942bacb8) | exec_context.hh (2670:9107b8bd08cd) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; |
46class EndQuiesceEvent; |
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46class Event; 47class TranslatingPort; 48class FunctionalPort; 49class VirtualPort; 50class Process; 51class System; | 47class Event; 48class TranslatingPort; 49class FunctionalPort; 50class VirtualPort; 51class Process; 52class System; |
53namespace Kernel { 54 class Statistics; 55}; |
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52 53class ExecContext 54{ 55 protected: 56 typedef TheISA::RegFile RegFile; 57 typedef TheISA::MachInst MachInst; 58 typedef TheISA::IntReg IntReg; 59 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 93 94#if FULL_SYSTEM 95 virtual System *getSystemPtr() = 0; 96 97 virtual AlphaITB *getITBPtr() = 0; 98 99 virtual AlphaDTB * getDTBPtr() = 0; 100 | 56 57class ExecContext 58{ 59 protected: 60 typedef TheISA::RegFile RegFile; 61 typedef TheISA::MachInst MachInst; 62 typedef TheISA::IntReg IntReg; 63 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 97 98#if FULL_SYSTEM 99 virtual System *getSystemPtr() = 0; 100 101 virtual AlphaITB *getITBPtr() = 0; 102 103 virtual AlphaDTB * getDTBPtr() = 0; 104 |
105 virtual Kernel::Statistics *getKernelStats() = 0; 106 |
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101 virtual FunctionalPort *getPhysPort() = 0; 102 103 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 104 105 virtual void delVirtPort(VirtualPort *vp) = 0; 106#else 107 virtual TranslatingPort *getMemPort() = 0; 108 --- 24 unchanged lines hidden (view full) --- 133 virtual void takeOverFrom(ExecContext *old_context) = 0; 134 135 virtual void regStats(const std::string &name) = 0; 136 137 virtual void serialize(std::ostream &os) = 0; 138 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 139 140#if FULL_SYSTEM | 107 virtual FunctionalPort *getPhysPort() = 0; 108 109 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 110 111 virtual void delVirtPort(VirtualPort *vp) = 0; 112#else 113 virtual TranslatingPort *getMemPort() = 0; 114 --- 24 unchanged lines hidden (view full) --- 139 virtual void takeOverFrom(ExecContext *old_context) = 0; 140 141 virtual void regStats(const std::string &name) = 0; 142 143 virtual void serialize(std::ostream &os) = 0; 144 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 145 146#if FULL_SYSTEM |
141 virtual Event *getQuiesceEvent() = 0; | 147 virtual EndQuiesceEvent *getQuiesceEvent() = 0; |
142 143 // Not necessarily the best location for these... 144 // Having an extra function just to read these is obnoxious 145 virtual Tick readLastActivate() = 0; 146 virtual Tick readLastSuspend() = 0; 147 148 virtual void profileClear() = 0; 149 virtual void profileSample() = 0; 150#endif 151 152 virtual int getThreadNum() = 0; 153 | 148 149 // Not necessarily the best location for these... 150 // Having an extra function just to read these is obnoxious 151 virtual Tick readLastActivate() = 0; 152 virtual Tick readLastSuspend() = 0; 153 154 virtual void profileClear() = 0; 155 virtual void profileSample() = 0; 156#endif 157 158 virtual int getThreadNum() = 0; 159 |
154 virtual int getInstAsid() = 0; 155 virtual int getDataAsid() = 0; 156 157 virtual Fault translateInstReq(RequestPtr &req) = 0; 158 159 virtual Fault translateDataReadReq(RequestPtr &req) = 0; 160 161 virtual Fault translateDataWriteReq(RequestPtr &req) = 0; 162 | |
163 // Also somewhat obnoxious. Really only used for the TLB fault. 164 // However, may be quite useful in SPARC. 165 virtual TheISA::MachInst getInst() = 0; 166 167 virtual void copyArchRegs(ExecContext *xc) = 0; 168 169 virtual void clearArchRegs() = 0; 170 --- 42 unchanged lines hidden (view full) --- 213 214 // Also not necessarily the best location for these two. Hopefully will go 215 // away once we decide upon where st cond failures goes. 216 virtual unsigned readStCondFailures() = 0; 217 218 virtual void setStCondFailures(unsigned sc_failures) = 0; 219 220#if FULL_SYSTEM | 160 // Also somewhat obnoxious. Really only used for the TLB fault. 161 // However, may be quite useful in SPARC. 162 virtual TheISA::MachInst getInst() = 0; 163 164 virtual void copyArchRegs(ExecContext *xc) = 0; 165 166 virtual void clearArchRegs() = 0; 167 --- 42 unchanged lines hidden (view full) --- 210 211 // Also not necessarily the best location for these two. Hopefully will go 212 // away once we decide upon where st cond failures goes. 213 virtual unsigned readStCondFailures() = 0; 214 215 virtual void setStCondFailures(unsigned sc_failures) = 0; 216 217#if FULL_SYSTEM |
221 virtual int readIntrFlag() = 0; 222 virtual void setIntrFlag(int val) = 0; 223 virtual Fault hwrei() = 0; | |
224 virtual bool inPalMode() = 0; | 218 virtual bool inPalMode() = 0; |
225 virtual bool simPalCheck(int palFunc) = 0; | |
226#endif 227 228 // Only really makes sense for old CPU model. Still could be useful though. 229 virtual bool misspeculating() = 0; 230 231#if !FULL_SYSTEM 232 virtual IntReg getSyscallArg(int i) = 0; 233 234 // used to shift args for indirect syscall 235 virtual void setSyscallArg(int i, IntReg val) = 0; 236 237 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 238 | 219#endif 220 221 // Only really makes sense for old CPU model. Still could be useful though. 222 virtual bool misspeculating() = 0; 223 224#if !FULL_SYSTEM 225 virtual IntReg getSyscallArg(int i) = 0; 226 227 // used to shift args for indirect syscall 228 virtual void setSyscallArg(int i, IntReg val) = 0; 229 230 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 231 |
239 virtual void syscall(int64_t callnum) = 0; | |
240 241 // Same with st cond failures. 242 virtual Counter readFuncExeInst() = 0; | 232 233 // Same with st cond failures. 234 virtual Counter readFuncExeInst() = 0; |
243 244 virtual void setFuncExeInst(Counter new_val) = 0; | |
245#endif 246 247 virtual void changeRegFileContext(RegFile::ContextParam param, 248 RegFile::ContextVal val) = 0; 249}; 250 251template <class XC> 252class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 268 269#if FULL_SYSTEM 270 System *getSystemPtr() { return actualXC->getSystemPtr(); } 271 272 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 273 274 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 275 | 235#endif 236 237 virtual void changeRegFileContext(RegFile::ContextParam param, 238 RegFile::ContextVal val) = 0; 239}; 240 241template <class XC> 242class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 258 259#if FULL_SYSTEM 260 System *getSystemPtr() { return actualXC->getSystemPtr(); } 261 262 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 263 264 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 265 |
266 Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } 267 |
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276 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 277 278 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 279 280 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 281#else 282 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 283 --- 26 unchanged lines hidden (view full) --- 310 311 void regStats(const std::string &name) { actualXC->regStats(name); } 312 313 void serialize(std::ostream &os) { actualXC->serialize(os); } 314 void unserialize(Checkpoint *cp, const std::string §ion) 315 { actualXC->unserialize(cp, section); } 316 317#if FULL_SYSTEM | 268 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 269 270 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 271 272 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 273#else 274 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 275 --- 26 unchanged lines hidden (view full) --- 302 303 void regStats(const std::string &name) { actualXC->regStats(name); } 304 305 void serialize(std::ostream &os) { actualXC->serialize(os); } 306 void unserialize(Checkpoint *cp, const std::string §ion) 307 { actualXC->unserialize(cp, section); } 308 309#if FULL_SYSTEM |
318 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } | 310 EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } |
319 320 Tick readLastActivate() { return actualXC->readLastActivate(); } 321 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 322 323 void profileClear() { return actualXC->profileClear(); } 324 void profileSample() { return actualXC->profileSample(); } 325#endif 326 327 int getThreadNum() { return actualXC->getThreadNum(); } 328 | 311 312 Tick readLastActivate() { return actualXC->readLastActivate(); } 313 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 314 315 void profileClear() { return actualXC->profileClear(); } 316 void profileSample() { return actualXC->profileSample(); } 317#endif 318 319 int getThreadNum() { return actualXC->getThreadNum(); } 320 |
329 int getInstAsid() { return actualXC->getInstAsid(); } 330 int getDataAsid() { return actualXC->getDataAsid(); } 331 332 Fault translateInstReq(RequestPtr &req) 333 { return actualXC->translateInstReq(req); } 334 335 Fault translateDataReadReq(RequestPtr &req) 336 { return actualXC->translateDataReadReq(req); } 337 338 Fault translateDataWriteReq(RequestPtr &req) 339 { return actualXC->translateDataWriteReq(req); } 340 | |
341 // @todo: Do I need this? 342 MachInst getInst() { return actualXC->getInst(); } 343 344 // @todo: Do I need this? 345 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 346 347 void clearArchRegs() { actualXC->clearArchRegs(); } 348 --- 54 unchanged lines hidden (view full) --- 403 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 404 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 405 406 unsigned readStCondFailures() 407 { return actualXC->readStCondFailures(); } 408 409 void setStCondFailures(unsigned sc_failures) 410 { actualXC->setStCondFailures(sc_failures); } | 321 // @todo: Do I need this? 322 MachInst getInst() { return actualXC->getInst(); } 323 324 // @todo: Do I need this? 325 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 326 327 void clearArchRegs() { actualXC->clearArchRegs(); } 328 --- 54 unchanged lines hidden (view full) --- 383 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 384 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 385 386 unsigned readStCondFailures() 387 { return actualXC->readStCondFailures(); } 388 389 void setStCondFailures(unsigned sc_failures) 390 { actualXC->setStCondFailures(sc_failures); } |
411 | |
412#if FULL_SYSTEM | 391#if FULL_SYSTEM |
413 int readIntrFlag() { return actualXC->readIntrFlag(); } 414 415 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 416 417 Fault hwrei() { return actualXC->hwrei(); } 418 | |
419 bool inPalMode() { return actualXC->inPalMode(); } | 392 bool inPalMode() { return actualXC->inPalMode(); } |
420 421 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } | |
422#endif 423 424 // @todo: Fix this! 425 bool misspeculating() { return actualXC->misspeculating(); } 426 427#if !FULL_SYSTEM 428 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 429 430 // used to shift args for indirect syscall 431 void setSyscallArg(int i, IntReg val) 432 { actualXC->setSyscallArg(i, val); } 433 434 void setSyscallReturn(SyscallReturn return_value) 435 { actualXC->setSyscallReturn(return_value); } 436 | 393#endif 394 395 // @todo: Fix this! 396 bool misspeculating() { return actualXC->misspeculating(); } 397 398#if !FULL_SYSTEM 399 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 400 401 // used to shift args for indirect syscall 402 void setSyscallArg(int i, IntReg val) 403 { actualXC->setSyscallArg(i, val); } 404 405 void setSyscallReturn(SyscallReturn return_value) 406 { actualXC->setSyscallReturn(return_value); } 407 |
437 void syscall(int64_t callnum) { actualXC->syscall(callnum); } | |
438 439 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } | 408 409 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } |
440 441 void setFuncExeInst(Counter new_val) 442 { return actualXC->setFuncExeInst(new_val); } | |
443#endif 444 445 void changeRegFileContext(RegFile::ContextParam param, 446 RegFile::ContextVal val) 447 { 448 actualXC->changeRegFileContext(param, val); 449 } 450}; 451 452#endif | 410#endif 411 412 void changeRegFileContext(RegFile::ContextParam param, 413 RegFile::ContextVal val) 414 { 415 actualXC->changeRegFileContext(param, val); 416 } 417}; 418 419#endif |