exec_context.hh (2654:9559cfa91b9d) | exec_context.hh (2665:a124942bacb8) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 10 unchanged lines hidden (view full) --- 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
27 * 28 * Authors: Kevin Lim |
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27 */ 28 29#ifndef __CPU_EXEC_CONTEXT_HH__ 30#define __CPU_EXEC_CONTEXT_HH__ 31 32#include "config/full_system.hh" 33#include "mem/request.hh" 34#include "sim/faults.hh" 35#include "sim/host.hh" 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// @todo: Figure out a more architecture independent way to obtain the ITB and 40// DTB pointers. 41class AlphaDTB; 42class AlphaITB; 43class BaseCPU; | 29 */ 30 31#ifndef __CPU_EXEC_CONTEXT_HH__ 32#define __CPU_EXEC_CONTEXT_HH__ 33 34#include "config/full_system.hh" 35#include "mem/request.hh" 36#include "sim/faults.hh" 37#include "sim/host.hh" 38#include "sim/serialize.hh" 39#include "sim/byteswap.hh" 40 41// @todo: Figure out a more architecture independent way to obtain the ITB and 42// DTB pointers. 43class AlphaDTB; 44class AlphaITB; 45class BaseCPU; |
44class EndQuiesceEvent; | |
45class Event; 46class TranslatingPort; 47class FunctionalPort; 48class VirtualPort; 49class Process; 50class System; | 46class Event; 47class TranslatingPort; 48class FunctionalPort; 49class VirtualPort; 50class Process; 51class System; |
51namespace Kernel { 52 class Statistics; 53}; | |
54 55class ExecContext 56{ 57 protected: 58 typedef TheISA::RegFile RegFile; 59 typedef TheISA::MachInst MachInst; 60 typedef TheISA::IntReg IntReg; 61 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 95 96#if FULL_SYSTEM 97 virtual System *getSystemPtr() = 0; 98 99 virtual AlphaITB *getITBPtr() = 0; 100 101 virtual AlphaDTB * getDTBPtr() = 0; 102 | 52 53class ExecContext 54{ 55 protected: 56 typedef TheISA::RegFile RegFile; 57 typedef TheISA::MachInst MachInst; 58 typedef TheISA::IntReg IntReg; 59 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 93 94#if FULL_SYSTEM 95 virtual System *getSystemPtr() = 0; 96 97 virtual AlphaITB *getITBPtr() = 0; 98 99 virtual AlphaDTB * getDTBPtr() = 0; 100 |
103 virtual Kernel::Statistics *getKernelStats() = 0; 104 | |
105 virtual FunctionalPort *getPhysPort() = 0; 106 107 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 108 109 virtual void delVirtPort(VirtualPort *vp) = 0; 110#else 111 virtual TranslatingPort *getMemPort() = 0; 112 --- 24 unchanged lines hidden (view full) --- 137 virtual void takeOverFrom(ExecContext *old_context) = 0; 138 139 virtual void regStats(const std::string &name) = 0; 140 141 virtual void serialize(std::ostream &os) = 0; 142 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 143 144#if FULL_SYSTEM | 101 virtual FunctionalPort *getPhysPort() = 0; 102 103 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 104 105 virtual void delVirtPort(VirtualPort *vp) = 0; 106#else 107 virtual TranslatingPort *getMemPort() = 0; 108 --- 24 unchanged lines hidden (view full) --- 133 virtual void takeOverFrom(ExecContext *old_context) = 0; 134 135 virtual void regStats(const std::string &name) = 0; 136 137 virtual void serialize(std::ostream &os) = 0; 138 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 139 140#if FULL_SYSTEM |
145 virtual EndQuiesceEvent *getQuiesceEvent() = 0; | 141 virtual Event *getQuiesceEvent() = 0; |
146 147 // Not necessarily the best location for these... 148 // Having an extra function just to read these is obnoxious 149 virtual Tick readLastActivate() = 0; 150 virtual Tick readLastSuspend() = 0; 151 152 virtual void profileClear() = 0; 153 virtual void profileSample() = 0; 154#endif 155 156 virtual int getThreadNum() = 0; 157 | 142 143 // Not necessarily the best location for these... 144 // Having an extra function just to read these is obnoxious 145 virtual Tick readLastActivate() = 0; 146 virtual Tick readLastSuspend() = 0; 147 148 virtual void profileClear() = 0; 149 virtual void profileSample() = 0; 150#endif 151 152 virtual int getThreadNum() = 0; 153 |
154 virtual int getInstAsid() = 0; 155 virtual int getDataAsid() = 0; 156 157 virtual Fault translateInstReq(RequestPtr &req) = 0; 158 159 virtual Fault translateDataReadReq(RequestPtr &req) = 0; 160 161 virtual Fault translateDataWriteReq(RequestPtr &req) = 0; 162 |
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158 // Also somewhat obnoxious. Really only used for the TLB fault. 159 // However, may be quite useful in SPARC. 160 virtual TheISA::MachInst getInst() = 0; 161 162 virtual void copyArchRegs(ExecContext *xc) = 0; 163 164 virtual void clearArchRegs() = 0; 165 --- 42 unchanged lines hidden (view full) --- 208 209 // Also not necessarily the best location for these two. Hopefully will go 210 // away once we decide upon where st cond failures goes. 211 virtual unsigned readStCondFailures() = 0; 212 213 virtual void setStCondFailures(unsigned sc_failures) = 0; 214 215#if FULL_SYSTEM | 163 // Also somewhat obnoxious. Really only used for the TLB fault. 164 // However, may be quite useful in SPARC. 165 virtual TheISA::MachInst getInst() = 0; 166 167 virtual void copyArchRegs(ExecContext *xc) = 0; 168 169 virtual void clearArchRegs() = 0; 170 --- 42 unchanged lines hidden (view full) --- 213 214 // Also not necessarily the best location for these two. Hopefully will go 215 // away once we decide upon where st cond failures goes. 216 virtual unsigned readStCondFailures() = 0; 217 218 virtual void setStCondFailures(unsigned sc_failures) = 0; 219 220#if FULL_SYSTEM |
221 virtual int readIntrFlag() = 0; 222 virtual void setIntrFlag(int val) = 0; 223 virtual Fault hwrei() = 0; |
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216 virtual bool inPalMode() = 0; | 224 virtual bool inPalMode() = 0; |
225 virtual bool simPalCheck(int palFunc) = 0; |
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217#endif 218 219 // Only really makes sense for old CPU model. Still could be useful though. 220 virtual bool misspeculating() = 0; 221 222#if !FULL_SYSTEM 223 virtual IntReg getSyscallArg(int i) = 0; 224 225 // used to shift args for indirect syscall 226 virtual void setSyscallArg(int i, IntReg val) = 0; 227 228 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 229 | 226#endif 227 228 // Only really makes sense for old CPU model. Still could be useful though. 229 virtual bool misspeculating() = 0; 230 231#if !FULL_SYSTEM 232 virtual IntReg getSyscallArg(int i) = 0; 233 234 // used to shift args for indirect syscall 235 virtual void setSyscallArg(int i, IntReg val) = 0; 236 237 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 238 |
239 virtual void syscall(int64_t callnum) = 0; |
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230 231 // Same with st cond failures. 232 virtual Counter readFuncExeInst() = 0; | 240 241 // Same with st cond failures. 242 virtual Counter readFuncExeInst() = 0; |
243 244 virtual void setFuncExeInst(Counter new_val) = 0; |
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233#endif 234 235 virtual void changeRegFileContext(RegFile::ContextParam param, 236 RegFile::ContextVal val) = 0; 237}; 238 239template <class XC> 240class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 256 257#if FULL_SYSTEM 258 System *getSystemPtr() { return actualXC->getSystemPtr(); } 259 260 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 261 262 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 263 | 245#endif 246 247 virtual void changeRegFileContext(RegFile::ContextParam param, 248 RegFile::ContextVal val) = 0; 249}; 250 251template <class XC> 252class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 268 269#if FULL_SYSTEM 270 System *getSystemPtr() { return actualXC->getSystemPtr(); } 271 272 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 273 274 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 275 |
264 Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } 265 | |
266 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 267 268 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 269 270 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 271#else 272 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 273 --- 26 unchanged lines hidden (view full) --- 300 301 void regStats(const std::string &name) { actualXC->regStats(name); } 302 303 void serialize(std::ostream &os) { actualXC->serialize(os); } 304 void unserialize(Checkpoint *cp, const std::string §ion) 305 { actualXC->unserialize(cp, section); } 306 307#if FULL_SYSTEM | 276 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 277 278 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 279 280 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 281#else 282 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 283 --- 26 unchanged lines hidden (view full) --- 310 311 void regStats(const std::string &name) { actualXC->regStats(name); } 312 313 void serialize(std::ostream &os) { actualXC->serialize(os); } 314 void unserialize(Checkpoint *cp, const std::string §ion) 315 { actualXC->unserialize(cp, section); } 316 317#if FULL_SYSTEM |
308 EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } | 318 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } |
309 310 Tick readLastActivate() { return actualXC->readLastActivate(); } 311 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 312 313 void profileClear() { return actualXC->profileClear(); } 314 void profileSample() { return actualXC->profileSample(); } 315#endif 316 317 int getThreadNum() { return actualXC->getThreadNum(); } 318 | 319 320 Tick readLastActivate() { return actualXC->readLastActivate(); } 321 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 322 323 void profileClear() { return actualXC->profileClear(); } 324 void profileSample() { return actualXC->profileSample(); } 325#endif 326 327 int getThreadNum() { return actualXC->getThreadNum(); } 328 |
329 int getInstAsid() { return actualXC->getInstAsid(); } 330 int getDataAsid() { return actualXC->getDataAsid(); } 331 332 Fault translateInstReq(RequestPtr &req) 333 { return actualXC->translateInstReq(req); } 334 335 Fault translateDataReadReq(RequestPtr &req) 336 { return actualXC->translateDataReadReq(req); } 337 338 Fault translateDataWriteReq(RequestPtr &req) 339 { return actualXC->translateDataWriteReq(req); } 340 |
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319 // @todo: Do I need this? 320 MachInst getInst() { return actualXC->getInst(); } 321 322 // @todo: Do I need this? 323 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 324 325 void clearArchRegs() { actualXC->clearArchRegs(); } 326 --- 54 unchanged lines hidden (view full) --- 381 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 382 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 383 384 unsigned readStCondFailures() 385 { return actualXC->readStCondFailures(); } 386 387 void setStCondFailures(unsigned sc_failures) 388 { actualXC->setStCondFailures(sc_failures); } | 341 // @todo: Do I need this? 342 MachInst getInst() { return actualXC->getInst(); } 343 344 // @todo: Do I need this? 345 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 346 347 void clearArchRegs() { actualXC->clearArchRegs(); } 348 --- 54 unchanged lines hidden (view full) --- 403 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 404 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 405 406 unsigned readStCondFailures() 407 { return actualXC->readStCondFailures(); } 408 409 void setStCondFailures(unsigned sc_failures) 410 { actualXC->setStCondFailures(sc_failures); } |
411 |
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389#if FULL_SYSTEM | 412#if FULL_SYSTEM |
413 int readIntrFlag() { return actualXC->readIntrFlag(); } 414 415 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 416 417 Fault hwrei() { return actualXC->hwrei(); } 418 |
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390 bool inPalMode() { return actualXC->inPalMode(); } | 419 bool inPalMode() { return actualXC->inPalMode(); } |
420 421 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } |
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391#endif 392 393 // @todo: Fix this! 394 bool misspeculating() { return actualXC->misspeculating(); } 395 396#if !FULL_SYSTEM 397 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 398 399 // used to shift args for indirect syscall 400 void setSyscallArg(int i, IntReg val) 401 { actualXC->setSyscallArg(i, val); } 402 403 void setSyscallReturn(SyscallReturn return_value) 404 { actualXC->setSyscallReturn(return_value); } 405 | 422#endif 423 424 // @todo: Fix this! 425 bool misspeculating() { return actualXC->misspeculating(); } 426 427#if !FULL_SYSTEM 428 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 429 430 // used to shift args for indirect syscall 431 void setSyscallArg(int i, IntReg val) 432 { actualXC->setSyscallArg(i, val); } 433 434 void setSyscallReturn(SyscallReturn return_value) 435 { actualXC->setSyscallReturn(return_value); } 436 |
437 void syscall(int64_t callnum) { actualXC->syscall(callnum); } |
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406 407 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } | 438 439 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } |
440 441 void setFuncExeInst(Counter new_val) 442 { return actualXC->setFuncExeInst(new_val); } |
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408#endif 409 410 void changeRegFileContext(RegFile::ContextParam param, 411 RegFile::ContextVal val) 412 { 413 actualXC->changeRegFileContext(param, val); 414 } 415}; 416 417#endif | 443#endif 444 445 void changeRegFileContext(RegFile::ContextParam param, 446 RegFile::ContextVal val) 447 { 448 actualXC->changeRegFileContext(param, val); 449 } 450}; 451 452#endif |