exec_context.hh (2632:1bb2f91485ea) | exec_context.hh (2654:9559cfa91b9d) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// @todo: Figure out a more architecture independent way to obtain the ITB and 40// DTB pointers. 41class AlphaDTB; 42class AlphaITB; 43class BaseCPU; | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 27 unchanged lines hidden (view full) --- 36#include "sim/serialize.hh" 37#include "sim/byteswap.hh" 38 39// @todo: Figure out a more architecture independent way to obtain the ITB and 40// DTB pointers. 41class AlphaDTB; 42class AlphaITB; 43class BaseCPU; |
44class EndQuiesceEvent; |
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44class Event; 45class TranslatingPort; 46class FunctionalPort; 47class VirtualPort; 48class Process; 49class System; | 45class Event; 46class TranslatingPort; 47class FunctionalPort; 48class VirtualPort; 49class Process; 50class System; |
51namespace Kernel { 52 class Statistics; 53}; |
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50 51class ExecContext 52{ 53 protected: 54 typedef TheISA::RegFile RegFile; 55 typedef TheISA::MachInst MachInst; 56 typedef TheISA::IntReg IntReg; 57 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 91 92#if FULL_SYSTEM 93 virtual System *getSystemPtr() = 0; 94 95 virtual AlphaITB *getITBPtr() = 0; 96 97 virtual AlphaDTB * getDTBPtr() = 0; 98 | 54 55class ExecContext 56{ 57 protected: 58 typedef TheISA::RegFile RegFile; 59 typedef TheISA::MachInst MachInst; 60 typedef TheISA::IntReg IntReg; 61 typedef TheISA::FloatReg FloatReg; --- 33 unchanged lines hidden (view full) --- 95 96#if FULL_SYSTEM 97 virtual System *getSystemPtr() = 0; 98 99 virtual AlphaITB *getITBPtr() = 0; 100 101 virtual AlphaDTB * getDTBPtr() = 0; 102 |
103 virtual Kernel::Statistics *getKernelStats() = 0; 104 |
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99 virtual FunctionalPort *getPhysPort() = 0; 100 101 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 102 103 virtual void delVirtPort(VirtualPort *vp) = 0; 104#else 105 virtual TranslatingPort *getMemPort() = 0; 106 --- 24 unchanged lines hidden (view full) --- 131 virtual void takeOverFrom(ExecContext *old_context) = 0; 132 133 virtual void regStats(const std::string &name) = 0; 134 135 virtual void serialize(std::ostream &os) = 0; 136 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 137 138#if FULL_SYSTEM | 105 virtual FunctionalPort *getPhysPort() = 0; 106 107 virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0; 108 109 virtual void delVirtPort(VirtualPort *vp) = 0; 110#else 111 virtual TranslatingPort *getMemPort() = 0; 112 --- 24 unchanged lines hidden (view full) --- 137 virtual void takeOverFrom(ExecContext *old_context) = 0; 138 139 virtual void regStats(const std::string &name) = 0; 140 141 virtual void serialize(std::ostream &os) = 0; 142 virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 143 144#if FULL_SYSTEM |
139 virtual Event *getQuiesceEvent() = 0; | 145 virtual EndQuiesceEvent *getQuiesceEvent() = 0; |
140 141 // Not necessarily the best location for these... 142 // Having an extra function just to read these is obnoxious 143 virtual Tick readLastActivate() = 0; 144 virtual Tick readLastSuspend() = 0; 145 146 virtual void profileClear() = 0; 147 virtual void profileSample() = 0; 148#endif 149 150 virtual int getThreadNum() = 0; 151 | 146 147 // Not necessarily the best location for these... 148 // Having an extra function just to read these is obnoxious 149 virtual Tick readLastActivate() = 0; 150 virtual Tick readLastSuspend() = 0; 151 152 virtual void profileClear() = 0; 153 virtual void profileSample() = 0; 154#endif 155 156 virtual int getThreadNum() = 0; 157 |
152 virtual int getInstAsid() = 0; 153 virtual int getDataAsid() = 0; 154 155 virtual Fault translateInstReq(RequestPtr &req) = 0; 156 157 virtual Fault translateDataReadReq(RequestPtr &req) = 0; 158 159 virtual Fault translateDataWriteReq(RequestPtr &req) = 0; 160 | |
161 // Also somewhat obnoxious. Really only used for the TLB fault. 162 // However, may be quite useful in SPARC. 163 virtual TheISA::MachInst getInst() = 0; 164 165 virtual void copyArchRegs(ExecContext *xc) = 0; 166 167 virtual void clearArchRegs() = 0; 168 --- 42 unchanged lines hidden (view full) --- 211 212 // Also not necessarily the best location for these two. Hopefully will go 213 // away once we decide upon where st cond failures goes. 214 virtual unsigned readStCondFailures() = 0; 215 216 virtual void setStCondFailures(unsigned sc_failures) = 0; 217 218#if FULL_SYSTEM | 158 // Also somewhat obnoxious. Really only used for the TLB fault. 159 // However, may be quite useful in SPARC. 160 virtual TheISA::MachInst getInst() = 0; 161 162 virtual void copyArchRegs(ExecContext *xc) = 0; 163 164 virtual void clearArchRegs() = 0; 165 --- 42 unchanged lines hidden (view full) --- 208 209 // Also not necessarily the best location for these two. Hopefully will go 210 // away once we decide upon where st cond failures goes. 211 virtual unsigned readStCondFailures() = 0; 212 213 virtual void setStCondFailures(unsigned sc_failures) = 0; 214 215#if FULL_SYSTEM |
219 virtual int readIntrFlag() = 0; 220 virtual void setIntrFlag(int val) = 0; 221 virtual Fault hwrei() = 0; | |
222 virtual bool inPalMode() = 0; | 216 virtual bool inPalMode() = 0; |
223 virtual bool simPalCheck(int palFunc) = 0; | |
224#endif 225 226 // Only really makes sense for old CPU model. Still could be useful though. 227 virtual bool misspeculating() = 0; 228 229#if !FULL_SYSTEM 230 virtual IntReg getSyscallArg(int i) = 0; 231 232 // used to shift args for indirect syscall 233 virtual void setSyscallArg(int i, IntReg val) = 0; 234 235 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 236 | 217#endif 218 219 // Only really makes sense for old CPU model. Still could be useful though. 220 virtual bool misspeculating() = 0; 221 222#if !FULL_SYSTEM 223 virtual IntReg getSyscallArg(int i) = 0; 224 225 // used to shift args for indirect syscall 226 virtual void setSyscallArg(int i, IntReg val) = 0; 227 228 virtual void setSyscallReturn(SyscallReturn return_value) = 0; 229 |
237 virtual void syscall(int64_t callnum) = 0; | |
238 239 // Same with st cond failures. 240 virtual Counter readFuncExeInst() = 0; | 230 231 // Same with st cond failures. 232 virtual Counter readFuncExeInst() = 0; |
241 242 virtual void setFuncExeInst(Counter new_val) = 0; | |
243#endif 244 245 virtual void changeRegFileContext(RegFile::ContextParam param, 246 RegFile::ContextVal val) = 0; 247}; 248 249template <class XC> 250class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 266 267#if FULL_SYSTEM 268 System *getSystemPtr() { return actualXC->getSystemPtr(); } 269 270 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 271 272 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 273 | 233#endif 234 235 virtual void changeRegFileContext(RegFile::ContextParam param, 236 RegFile::ContextVal val) = 0; 237}; 238 239template <class XC> 240class ProxyExecContext : public ExecContext --- 15 unchanged lines hidden (view full) --- 256 257#if FULL_SYSTEM 258 System *getSystemPtr() { return actualXC->getSystemPtr(); } 259 260 AlphaITB *getITBPtr() { return actualXC->getITBPtr(); } 261 262 AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); } 263 |
264 Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); } 265 |
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274 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 275 276 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 277 278 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 279#else 280 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 281 --- 26 unchanged lines hidden (view full) --- 308 309 void regStats(const std::string &name) { actualXC->regStats(name); } 310 311 void serialize(std::ostream &os) { actualXC->serialize(os); } 312 void unserialize(Checkpoint *cp, const std::string §ion) 313 { actualXC->unserialize(cp, section); } 314 315#if FULL_SYSTEM | 266 FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); } 267 268 VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); } 269 270 void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); } 271#else 272 TranslatingPort *getMemPort() { return actualXC->getMemPort(); } 273 --- 26 unchanged lines hidden (view full) --- 300 301 void regStats(const std::string &name) { actualXC->regStats(name); } 302 303 void serialize(std::ostream &os) { actualXC->serialize(os); } 304 void unserialize(Checkpoint *cp, const std::string §ion) 305 { actualXC->unserialize(cp, section); } 306 307#if FULL_SYSTEM |
316 Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } | 308 EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); } |
317 318 Tick readLastActivate() { return actualXC->readLastActivate(); } 319 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 320 321 void profileClear() { return actualXC->profileClear(); } 322 void profileSample() { return actualXC->profileSample(); } 323#endif 324 325 int getThreadNum() { return actualXC->getThreadNum(); } 326 | 309 310 Tick readLastActivate() { return actualXC->readLastActivate(); } 311 Tick readLastSuspend() { return actualXC->readLastSuspend(); } 312 313 void profileClear() { return actualXC->profileClear(); } 314 void profileSample() { return actualXC->profileSample(); } 315#endif 316 317 int getThreadNum() { return actualXC->getThreadNum(); } 318 |
327 int getInstAsid() { return actualXC->getInstAsid(); } 328 int getDataAsid() { return actualXC->getDataAsid(); } 329 330 Fault translateInstReq(RequestPtr &req) 331 { return actualXC->translateInstReq(req); } 332 333 Fault translateDataReadReq(RequestPtr &req) 334 { return actualXC->translateDataReadReq(req); } 335 336 Fault translateDataWriteReq(RequestPtr &req) 337 { return actualXC->translateDataWriteReq(req); } 338 | |
339 // @todo: Do I need this? 340 MachInst getInst() { return actualXC->getInst(); } 341 342 // @todo: Do I need this? 343 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 344 345 void clearArchRegs() { actualXC->clearArchRegs(); } 346 --- 54 unchanged lines hidden (view full) --- 401 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 402 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 403 404 unsigned readStCondFailures() 405 { return actualXC->readStCondFailures(); } 406 407 void setStCondFailures(unsigned sc_failures) 408 { actualXC->setStCondFailures(sc_failures); } | 319 // @todo: Do I need this? 320 MachInst getInst() { return actualXC->getInst(); } 321 322 // @todo: Do I need this? 323 void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); } 324 325 void clearArchRegs() { actualXC->clearArchRegs(); } 326 --- 54 unchanged lines hidden (view full) --- 381 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) 382 { return actualXC->setMiscRegWithEffect(misc_reg, val); } 383 384 unsigned readStCondFailures() 385 { return actualXC->readStCondFailures(); } 386 387 void setStCondFailures(unsigned sc_failures) 388 { actualXC->setStCondFailures(sc_failures); } |
409 | |
410#if FULL_SYSTEM | 389#if FULL_SYSTEM |
411 int readIntrFlag() { return actualXC->readIntrFlag(); } 412 413 void setIntrFlag(int val) { actualXC->setIntrFlag(val); } 414 415 Fault hwrei() { return actualXC->hwrei(); } 416 | |
417 bool inPalMode() { return actualXC->inPalMode(); } | 390 bool inPalMode() { return actualXC->inPalMode(); } |
418 419 bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); } | |
420#endif 421 422 // @todo: Fix this! 423 bool misspeculating() { return actualXC->misspeculating(); } 424 425#if !FULL_SYSTEM 426 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 427 428 // used to shift args for indirect syscall 429 void setSyscallArg(int i, IntReg val) 430 { actualXC->setSyscallArg(i, val); } 431 432 void setSyscallReturn(SyscallReturn return_value) 433 { actualXC->setSyscallReturn(return_value); } 434 | 391#endif 392 393 // @todo: Fix this! 394 bool misspeculating() { return actualXC->misspeculating(); } 395 396#if !FULL_SYSTEM 397 IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); } 398 399 // used to shift args for indirect syscall 400 void setSyscallArg(int i, IntReg val) 401 { actualXC->setSyscallArg(i, val); } 402 403 void setSyscallReturn(SyscallReturn return_value) 404 { actualXC->setSyscallReturn(return_value); } 405 |
435 void syscall(int64_t callnum) { actualXC->syscall(callnum); } | |
436 437 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } | 406 407 Counter readFuncExeInst() { return actualXC->readFuncExeInst(); } |
438 439 void setFuncExeInst(Counter new_val) 440 { return actualXC->setFuncExeInst(new_val); } | |
441#endif 442 443 void changeRegFileContext(RegFile::ContextParam param, 444 RegFile::ContextVal val) 445 { 446 actualXC->changeRegFileContext(param, val); 447 } 448}; 449 450#endif | 408#endif 409 410 void changeRegFileContext(RegFile::ContextParam param, 411 RegFile::ContextVal val) 412 { 413 actualXC->changeRegFileContext(param, val); 414 } 415}; 416 417#endif |