exec_context.hh (13610:5d5404ac6288) exec_context.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
1/*
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 typedef TheISA::CCReg CCReg;
78 using VecRegContainer = TheISA::VecRegContainer;
79 using VecElem = TheISA::VecElem;
80 using VecPredRegContainer = TheISA::VecPredRegContainer;
81
82 public:
83 /**
84 * @{
85 * @name Integer Register Interfaces

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184 setVecPredRegOperand(const StaticInst *si, int idx,
185 const VecPredRegContainer& val) = 0;
186 /** @} */
187
188 /**
189 * @{
190 * @name Condition Code Registers
191 */
77 using VecRegContainer = TheISA::VecRegContainer;
78 using VecElem = TheISA::VecElem;
79 using VecPredRegContainer = TheISA::VecPredRegContainer;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces

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183 setVecPredRegOperand(const StaticInst *si, int idx,
184 const VecPredRegContainer& val) = 0;
185 /** @} */
186
187 /**
188 * @{
189 * @name Condition Code Registers
190 */
192 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
193 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
191 virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
192 virtual void setCCRegOperand(
193 const StaticInst *si, int idx, RegVal val) = 0;
194 /** @} */
195
196 /**
197 * @{
198 * @name Misc Register Interfaces
199 */
200 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
201 virtual void setMiscRegOperand(const StaticInst *si,

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195
196 /**
197 * @{
198 * @name Misc Register Interfaces
199 */
200 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
201 virtual void setMiscRegOperand(const StaticInst *si,

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