exec_context.hh (13582:989577bf6abc) exec_context.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2014, 2016 ARM Limited
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 typedef TheISA::CCReg CCReg;
78 using VecRegContainer = TheISA::VecRegContainer;
79 using VecElem = TheISA::VecElem;
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 typedef TheISA::CCReg CCReg;
78 using VecRegContainer = TheISA::VecRegContainer;
79 using VecElem = TheISA::VecElem;
80 using VecPredRegContainer = TheISA::VecPredRegContainer;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces
85 *
86 */
87

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163 virtual VecElem readVecElemOperand(const StaticInst *si,
164 int idx) const = 0;
165
166 /** Sets a vector register to a value. */
167 virtual void setVecElemOperand(const StaticInst *si, int idx,
168 const VecElem val) = 0;
169 /** @} */
170
81
82 public:
83 /**
84 * @{
85 * @name Integer Register Interfaces
86 *
87 */
88

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164 virtual VecElem readVecElemOperand(const StaticInst *si,
165 int idx) const = 0;
166
167 /** Sets a vector register to a value. */
168 virtual void setVecElemOperand(const StaticInst *si, int idx,
169 const VecElem val) = 0;
170 /** @} */
171
172 /** Predicate registers interface. */
173 /** @{ */
174 /** Reads source predicate register operand. */
175 virtual const VecPredRegContainer&
176 readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
177
178 /** Gets destination predicate register operand for modification. */
179 virtual VecPredRegContainer&
180 getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
181
182 /** Sets a destination predicate register operand to a value. */
183 virtual void
184 setVecPredRegOperand(const StaticInst *si, int idx,
185 const VecPredRegContainer& val) = 0;
186 /** @} */
187
171 /**
172 * @{
173 * @name Condition Code Registers
174 */
175 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
176 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
177 /** @} */
178

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189 * @{
190 * @name Condition Code Registers
191 */
192 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
193 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
194 /** @} */
195

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