1/* 2 * Copyright (c) 2014, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 58 unchanged lines hidden (view full) --- 67 * @note The methods in this class typically take a raw pointer to the 68 * StaticInst is provided instead of a ref-counted StaticInstPtr to 69 * reduce overhead as an argument. This is fine as long as the 70 * implementation doesn't copy the pointer into any long-term storage 71 * (which is pretty hard to imagine they would have reason to do). 72 */ 73class ExecContext { 74 public: |
75 typedef TheISA::PCState PCState; |
76 77 typedef TheISA::CCReg CCReg; 78 using VecRegContainer = TheISA::VecRegContainer; 79 using VecElem = TheISA::VecElem; 80 81 public: 82 /** 83 * @{ 84 * @name Integer Register Interfaces 85 * 86 */ 87 88 /** Reads an integer register. */ |
89 virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0; |
90 91 /** Sets an integer register to a value. */ 92 virtual void setIntRegOperand(const StaticInst *si, |
93 int idx, RegVal val) = 0; |
94 95 /** @} */ 96 97 98 /** 99 * @{ 100 * @name Floating Point Register Interfaces 101 */ 102 103 /** Reads a floating point register in its binary format, instead 104 * of by value. */ |
105 virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0; |
106 107 /** Sets the bits of a floating point register of single width 108 * to a binary value. */ 109 virtual void setFloatRegOperandBits(const StaticInst *si, |
110 int idx, RegVal val) = 0; |
111 112 /** @} */ 113 114 /** Vector Register Interfaces. */ 115 /** @{ */ 116 /** Reads source vector register operand. */ 117 virtual const VecRegContainer& 118 readVecRegOperand(const StaticInst *si, int idx) const = 0; --- 56 unchanged lines hidden (view full) --- 175 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0; 176 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0; 177 /** @} */ 178 179 /** 180 * @{ 181 * @name Misc Register Interfaces 182 */ |
183 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0; |
184 virtual void setMiscRegOperand(const StaticInst *si, |
185 int idx, const RegVal &val) = 0; |
186 187 /** 188 * Reads a miscellaneous register, handling any architectural 189 * side effects due to reading that register. 190 */ |
191 virtual RegVal readMiscReg(int misc_reg) = 0; |
192 193 /** 194 * Sets a miscellaneous register, handling any architectural 195 * side effects due to writing that register. 196 */ |
197 virtual void setMiscReg(int misc_reg, const RegVal &val) = 0; |
198 199 /** @} */ 200 201 /** 202 * @{ 203 * @name PC Control 204 */ 205 virtual PCState pcState() const = 0; --- 110 unchanged lines hidden (view full) --- 316 /** @} */ 317 318 /** 319 * @{ 320 * @name MIPS-Specific Interfaces 321 */ 322 323#if THE_ISA == MIPS_ISA |
324 virtual RegVal readRegOtherThread(const RegId ®, 325 ThreadID tid=InvalidThreadID) = 0; 326 virtual void setRegOtherThread(const RegId& reg, RegVal val, 327 ThreadID tid=InvalidThreadID) = 0; |
328#endif 329 330 /** @} */ 331}; 332 333#endif // __CPU_EXEC_CONTEXT_HH__ |