1/* 2 * Copyright (c) 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 35 unchanged lines hidden (view full) --- 44 45#ifndef __CPU_EXEC_CONTEXT_HH__ 46#define __CPU_EXEC_CONTEXT_HH__ 47 48#include "arch/registers.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "cpu/base.hh" |
52#include "cpu/reg_class.hh" |
53#include "cpu/static_inst_fwd.hh" 54#include "cpu/translation.hh" 55#include "mem/request.hh" 56 57/** 58 * The ExecContext is an abstract base class the provides the 59 * interface used by the ISA to manipulate the state of the CPU model. 60 * --- 221 unchanged lines hidden (view full) --- 282 /** @} */ 283 284 /** 285 * @{ 286 * @name MIPS-Specific Interfaces 287 */ 288 289#if THE_ISA == MIPS_ISA |
290 virtual MiscReg readRegOtherThread(RegId reg, |
291 ThreadID tid = InvalidThreadID) = 0; |
292 virtual void setRegOtherThread(RegId reg, MiscReg val, |
293 ThreadID tid = InvalidThreadID) = 0; 294#endif 295 296 /** @} */ 297}; 298 299#endif // __CPU_EXEC_CONTEXT_HH__ |