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< * Copyright (c) 2014, 2016 ARM Limited
---
> * Copyright (c) 2014, 2016-2017 ARM Limited
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> using VecPredRegContainer = TheISA::VecPredRegContainer;
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> /** Predicate registers interface. */
> /** @{ */
> /** Reads source predicate register operand. */
> virtual const VecPredRegContainer&
> readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
>
> /** Gets destination predicate register operand for modification. */
> virtual VecPredRegContainer&
> getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
>
> /** Sets a destination predicate register operand to a value. */
> virtual void
> setVecPredRegOperand(const StaticInst *si, int idx,
> const VecPredRegContainer& val) = 0;
> /** @} */
>