1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#error "Cannot include this file" 32 33/** 34 * The ExecContext is not a usable class. It is simply here for 35 * documentation purposes. It shows the interface that is used by the 36 * ISA to access and change CPU state. 37 */ 38class ExecContext { 39 // The register accessor methods provide the index of the 40 // instruction's operand (e.g., 0 or 1), not the architectural 41 // register index, to simplify the implementation of register 42 // renaming. We find the architectural register index by indexing 43 // into the instruction's own operand index table. Note that a 44 // raw pointer to the StaticInst is provided instead of a 45 // ref-counted StaticInstPtr to reduce overhead. This is fine as 46 // long as these methods don't copy the pointer into any long-term 47 // storage (which is pretty hard to imagine they would have reason 48 // to do). 49 50 /** Reads an integer register. */
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#error "Cannot include this file" 32 33/** 34 * The ExecContext is not a usable class. It is simply here for 35 * documentation purposes. It shows the interface that is used by the 36 * ISA to access and change CPU state. 37 */ 38class ExecContext { 39 // The register accessor methods provide the index of the 40 // instruction's operand (e.g., 0 or 1), not the architectural 41 // register index, to simplify the implementation of register 42 // renaming. We find the architectural register index by indexing 43 // into the instruction's own operand index table. Note that a 44 // raw pointer to the StaticInst is provided instead of a 45 // ref-counted StaticInstPtr to reduce overhead. This is fine as 46 // long as these methods don't copy the pointer into any long-term 47 // storage (which is pretty hard to imagine they would have reason 48 // to do). 49 50 /** Reads an integer register. */
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51 uint64_t readIntReg(const StaticInst *si, int idx);
| 51 uint64_t readIntRegOperand(const StaticInst *si, int idx);
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52 53 /** Reads a floating point register of a specific width. */
| 52 53 /** Reads a floating point register of a specific width. */
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54 FloatReg readFloatReg(const StaticInst *si, int idx, int width);
| 54 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
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55 56 /** Reads a floating point register of single register width. */
| 55 56 /** Reads a floating point register of single register width. */
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57 FloatReg readFloatReg(const StaticInst *si, int idx);
| 57 FloatReg readFloatRegOperand(const StaticInst *si, int idx);
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58 59 /** Reads a floating point register of a specific width in its 60 * binary format, instead of by value. */
| 58 59 /** Reads a floating point register of a specific width in its 60 * binary format, instead of by value. */
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61 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
| 61 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, 62 int width);
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62 63 /** Reads a floating point register in its binary format, instead 64 * of by value. */
| 63 64 /** Reads a floating point register in its binary format, instead 65 * of by value. */
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65 FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
| 66 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
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66 67 /** Sets an integer register to a value. */
| 67 68 /** Sets an integer register to a value. */
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68 void setIntReg(const StaticInst *si, int idx, uint64_t val);
| 69 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
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69 70 /** Sets a floating point register of a specific width to a value. */
| 70 71 /** Sets a floating point register of a specific width to a value. */
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71 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
| 72 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, 73 int width);
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72 73 /** Sets a floating point register of single width to a value. */
| 74 75 /** Sets a floating point register of single width to a value. */
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74 void setFloatReg(const StaticInst *si, int idx, FloatReg val);
| 76 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
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75 76 /** Sets the bits of a floating point register of a specific width 77 * to a binary value. */
| 77 78 /** Sets the bits of a floating point register of a specific width 79 * to a binary value. */
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78 void setFloatRegBits(const StaticInst *si, int idx, 79 FloatRegBits val, int width);
| 80 void setFloatRegOperandBits(const StaticInst *si, int idx, 81 FloatRegBits val, int width);
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80 81 /** Sets the bits of a floating point register of single width 82 * to a binary value. */
| 82 83 /** Sets the bits of a floating point register of single width 84 * to a binary value. */
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83 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
| 85 void setFloatRegOperandBits(const StaticInst *si, int idx, 86 FloatRegBits val);
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84 85 /** Reads the PC. */ 86 uint64_t readPC(); 87 /** Reads the NextPC. */ 88 uint64_t readNextPC(); 89 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 90 uint64_t readNextNPC(); 91 92 /** Sets the PC. */ 93 void setPC(uint64_t val); 94 /** Sets the NextPC. */ 95 void setNextPC(uint64_t val); 96 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 97 void setNextNPC(uint64_t val); 98 99 /** Reads a miscellaneous register. */ 100 MiscReg readMiscReg(int misc_reg); 101 102 /** Reads a miscellaneous register, handling any architectural 103 * side effects due to reading that register. */ 104 MiscReg readMiscRegWithEffect(int misc_reg); 105 106 /** Sets a miscellaneous register. */ 107 void setMiscReg(int misc_reg, const MiscReg &val); 108 109 /** Sets a miscellaneous register, handling any architectural 110 * side effects due to writing that register. */ 111 void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 112 113 /** Records the effective address of the instruction. Only valid 114 * for memory ops. */ 115 void setEA(Addr EA); 116 /** Returns the effective address of the instruction. Only valid 117 * for memory ops. */ 118 Addr getEA(); 119 120 /** Returns a pointer to the ThreadContext. */ 121 ThreadContext *tcBase(); 122 123 /** Reads an address, creating a memory request with the given 124 * flags. Stores result of read in data. */ 125 template <class T> 126 Fault read(Addr addr, T &data, unsigned flags); 127 128 /** Writes to an address, creating a memory request with the given 129 * flags. Writes data to memory. For store conditionals, returns 130 * the result of the store in res. */ 131 template <class T> 132 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 133 134 /** Prefetches an address, creating a memory request with the 135 * given flags. */ 136 void prefetch(Addr addr, unsigned flags); 137 138 /** Hints to the memory system that an address will be written to 139 * soon, with the given size. Creates a memory request with the 140 * given flags. */ 141 void writeHint(Addr addr, int size, unsigned flags); 142 143#if FULL_SYSTEM 144 /** Somewhat Alpha-specific function that handles returning from 145 * an error or interrupt. */ 146 Fault hwrei(); 147 148 /** 149 * Check for special simulator handling of specific PAL calls. If 150 * return value is false, actual PAL call will be suppressed. 151 */ 152 bool simPalCheck(int palFunc); 153#else 154 /** Executes a syscall specified by the callnum. */ 155 void syscall(int64_t callnum); 156#endif 157};
| 87 88 /** Reads the PC. */ 89 uint64_t readPC(); 90 /** Reads the NextPC. */ 91 uint64_t readNextPC(); 92 /** Reads the Next-NextPC. Only for architectures like SPARC or MIPS. */ 93 uint64_t readNextNPC(); 94 95 /** Sets the PC. */ 96 void setPC(uint64_t val); 97 /** Sets the NextPC. */ 98 void setNextPC(uint64_t val); 99 /** Sets the Next-NextPC. Only for architectures like SPARC or MIPS. */ 100 void setNextNPC(uint64_t val); 101 102 /** Reads a miscellaneous register. */ 103 MiscReg readMiscReg(int misc_reg); 104 105 /** Reads a miscellaneous register, handling any architectural 106 * side effects due to reading that register. */ 107 MiscReg readMiscRegWithEffect(int misc_reg); 108 109 /** Sets a miscellaneous register. */ 110 void setMiscReg(int misc_reg, const MiscReg &val); 111 112 /** Sets a miscellaneous register, handling any architectural 113 * side effects due to writing that register. */ 114 void setMiscRegWithEffect(int misc_reg, const MiscReg &val); 115 116 /** Records the effective address of the instruction. Only valid 117 * for memory ops. */ 118 void setEA(Addr EA); 119 /** Returns the effective address of the instruction. Only valid 120 * for memory ops. */ 121 Addr getEA(); 122 123 /** Returns a pointer to the ThreadContext. */ 124 ThreadContext *tcBase(); 125 126 /** Reads an address, creating a memory request with the given 127 * flags. Stores result of read in data. */ 128 template <class T> 129 Fault read(Addr addr, T &data, unsigned flags); 130 131 /** Writes to an address, creating a memory request with the given 132 * flags. Writes data to memory. For store conditionals, returns 133 * the result of the store in res. */ 134 template <class T> 135 Fault write(T data, Addr addr, unsigned flags, uint64_t *res); 136 137 /** Prefetches an address, creating a memory request with the 138 * given flags. */ 139 void prefetch(Addr addr, unsigned flags); 140 141 /** Hints to the memory system that an address will be written to 142 * soon, with the given size. Creates a memory request with the 143 * given flags. */ 144 void writeHint(Addr addr, int size, unsigned flags); 145 146#if FULL_SYSTEM 147 /** Somewhat Alpha-specific function that handles returning from 148 * an error or interrupt. */ 149 Fault hwrei(); 150 151 /** 152 * Check for special simulator handling of specific PAL calls. If 153 * return value is false, actual PAL call will be suppressed. 154 */ 155 bool simPalCheck(int palFunc); 156#else 157 /** Executes a syscall specified by the callnum. */ 158 void syscall(int64_t callnum); 159#endif 160};
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