1/*
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming. The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 using VecRegContainer = TheISA::VecRegContainer;
78 using VecElem = TheISA::VecElem;
79 using VecPredRegContainer = TheISA::VecPredRegContainer;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces
85 *
86 */
87
88 /** Reads an integer register. */
89 virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
90
91 /** Sets an integer register to a value. */
92 virtual void setIntRegOperand(const StaticInst *si,
93 int idx, RegVal val) = 0;
94
95 /** @} */
96
97
98 /**
99 * @{
100 * @name Floating Point Register Interfaces
101 */
102
103 /** Reads a floating point register in its binary format, instead
104 * of by value. */
105 virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
106
107 /** Sets the bits of a floating point register of single width
108 * to a binary value. */
109 virtual void setFloatRegOperandBits(const StaticInst *si,
110 int idx, RegVal val) = 0;
111
112 /** @} */
113
114 /** Vector Register Interfaces. */
115 /** @{ */
116 /** Reads source vector register operand. */
117 virtual const VecRegContainer&
118 readVecRegOperand(const StaticInst *si, int idx) const = 0;
119
120 /** Gets destination vector register operand for modification. */
121 virtual VecRegContainer&
122 getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
123
124 /** Sets a destination vector register operand to a value. */
125 virtual void
126 setVecRegOperand(const StaticInst *si, int idx,
127 const VecRegContainer& val) = 0;
128 /** @} */
129
130 /** Vector Register Lane Interfaces. */
131 /** @{ */
132 /** Reads source vector 8bit operand. */
133 virtual ConstVecLane8
134 readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
135
136 /** Reads source vector 16bit operand. */
137 virtual ConstVecLane16
138 readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
139
140 /** Reads source vector 32bit operand. */
141 virtual ConstVecLane32
142 readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
143
144 /** Reads source vector 64bit operand. */
145 virtual ConstVecLane64
146 readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
147
148 /** Write a lane of the destination vector operand. */
149 /** @{ */
150 virtual void setVecLaneOperand(const StaticInst *si, int idx,
151 const LaneData<LaneSize::Byte>& val) = 0;
152 virtual void setVecLaneOperand(const StaticInst *si, int idx,
153 const LaneData<LaneSize::TwoByte>& val) = 0;
154 virtual void setVecLaneOperand(const StaticInst *si, int idx,
155 const LaneData<LaneSize::FourByte>& val) = 0;
156 virtual void setVecLaneOperand(const StaticInst *si, int idx,
157 const LaneData<LaneSize::EightByte>& val) = 0;
158 /** @} */
159
160 /** Vector Elem Interfaces. */
161 /** @{ */
162 /** Reads an element of a vector register. */
163 virtual VecElem readVecElemOperand(const StaticInst *si,
164 int idx) const = 0;
165
166 /** Sets a vector register to a value. */
167 virtual void setVecElemOperand(const StaticInst *si, int idx,
168 const VecElem val) = 0;
169 /** @} */
170
171 /** Predicate registers interface. */
172 /** @{ */
173 /** Reads source predicate register operand. */
174 virtual const VecPredRegContainer&
175 readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
176
177 /** Gets destination predicate register operand for modification. */
178 virtual VecPredRegContainer&
179 getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
180
181 /** Sets a destination predicate register operand to a value. */
182 virtual void
183 setVecPredRegOperand(const StaticInst *si, int idx,
184 const VecPredRegContainer& val) = 0;
185 /** @} */
186
187 /**
188 * @{
189 * @name Condition Code Registers
190 */
191 virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
192 virtual void setCCRegOperand(
193 const StaticInst *si, int idx, RegVal val) = 0;
194 /** @} */
195
196 /**
197 * @{
198 * @name Misc Register Interfaces
199 */
200 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
201 virtual void setMiscRegOperand(const StaticInst *si,
202 int idx, RegVal val) = 0;
203
204 /**
205 * Reads a miscellaneous register, handling any architectural
206 * side effects due to reading that register.
207 */
208 virtual RegVal readMiscReg(int misc_reg) = 0;
209
210 /**
211 * Sets a miscellaneous register, handling any architectural
212 * side effects due to writing that register.
213 */
214 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
215
216 /** @} */
217
218 /**
219 * @{
220 * @name PC Control
221 */
222 virtual PCState pcState() const = 0;
223 virtual void pcState(const PCState &val) = 0;
224 /** @} */
225
226 /**
227 * @{
228 * @name Memory Interface
229 */
230 /**
231 * Perform an atomic memory read operation. Must be overridden
232 * for exec contexts that support atomic memory mode. Not pure
233 * virtual since exec contexts that only support timing memory
234 * mode need not override (though in that case this function
235 * should never be called).
236 */
237 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
238 Request::Flags flags)
239 {
240 panic("ExecContext::readMem() should be overridden\n");
241 }
242
243 /**
244 * Initiate a timing memory read operation. Must be overridden
245 * for exec contexts that support timing memory mode. Not pure
246 * virtual since exec contexts that only support atomic memory
247 * mode need not override (though in that case this function
248 * should never be called).
249 */
250 virtual Fault initiateMemRead(Addr addr, unsigned int size,
251 Request::Flags flags)
252 {
253 panic("ExecContext::initiateMemRead() should be overridden\n");
254 }
255
256 /**
257 * For atomic-mode contexts, perform an atomic memory write operation.
258 * For timing-mode contexts, initiate a timing memory write operation.
259 */
260 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
261 Request::Flags flags, uint64_t *res) = 0;
262
263 /**
| 1/*
2 * Copyright (c) 2014, 2016-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming. The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 using VecRegContainer = TheISA::VecRegContainer;
78 using VecElem = TheISA::VecElem;
79 using VecPredRegContainer = TheISA::VecPredRegContainer;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces
85 *
86 */
87
88 /** Reads an integer register. */
89 virtual RegVal readIntRegOperand(const StaticInst *si, int idx) = 0;
90
91 /** Sets an integer register to a value. */
92 virtual void setIntRegOperand(const StaticInst *si,
93 int idx, RegVal val) = 0;
94
95 /** @} */
96
97
98 /**
99 * @{
100 * @name Floating Point Register Interfaces
101 */
102
103 /** Reads a floating point register in its binary format, instead
104 * of by value. */
105 virtual RegVal readFloatRegOperandBits(const StaticInst *si, int idx) = 0;
106
107 /** Sets the bits of a floating point register of single width
108 * to a binary value. */
109 virtual void setFloatRegOperandBits(const StaticInst *si,
110 int idx, RegVal val) = 0;
111
112 /** @} */
113
114 /** Vector Register Interfaces. */
115 /** @{ */
116 /** Reads source vector register operand. */
117 virtual const VecRegContainer&
118 readVecRegOperand(const StaticInst *si, int idx) const = 0;
119
120 /** Gets destination vector register operand for modification. */
121 virtual VecRegContainer&
122 getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
123
124 /** Sets a destination vector register operand to a value. */
125 virtual void
126 setVecRegOperand(const StaticInst *si, int idx,
127 const VecRegContainer& val) = 0;
128 /** @} */
129
130 /** Vector Register Lane Interfaces. */
131 /** @{ */
132 /** Reads source vector 8bit operand. */
133 virtual ConstVecLane8
134 readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
135
136 /** Reads source vector 16bit operand. */
137 virtual ConstVecLane16
138 readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
139
140 /** Reads source vector 32bit operand. */
141 virtual ConstVecLane32
142 readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
143
144 /** Reads source vector 64bit operand. */
145 virtual ConstVecLane64
146 readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
147
148 /** Write a lane of the destination vector operand. */
149 /** @{ */
150 virtual void setVecLaneOperand(const StaticInst *si, int idx,
151 const LaneData<LaneSize::Byte>& val) = 0;
152 virtual void setVecLaneOperand(const StaticInst *si, int idx,
153 const LaneData<LaneSize::TwoByte>& val) = 0;
154 virtual void setVecLaneOperand(const StaticInst *si, int idx,
155 const LaneData<LaneSize::FourByte>& val) = 0;
156 virtual void setVecLaneOperand(const StaticInst *si, int idx,
157 const LaneData<LaneSize::EightByte>& val) = 0;
158 /** @} */
159
160 /** Vector Elem Interfaces. */
161 /** @{ */
162 /** Reads an element of a vector register. */
163 virtual VecElem readVecElemOperand(const StaticInst *si,
164 int idx) const = 0;
165
166 /** Sets a vector register to a value. */
167 virtual void setVecElemOperand(const StaticInst *si, int idx,
168 const VecElem val) = 0;
169 /** @} */
170
171 /** Predicate registers interface. */
172 /** @{ */
173 /** Reads source predicate register operand. */
174 virtual const VecPredRegContainer&
175 readVecPredRegOperand(const StaticInst *si, int idx) const = 0;
176
177 /** Gets destination predicate register operand for modification. */
178 virtual VecPredRegContainer&
179 getWritableVecPredRegOperand(const StaticInst *si, int idx) = 0;
180
181 /** Sets a destination predicate register operand to a value. */
182 virtual void
183 setVecPredRegOperand(const StaticInst *si, int idx,
184 const VecPredRegContainer& val) = 0;
185 /** @} */
186
187 /**
188 * @{
189 * @name Condition Code Registers
190 */
191 virtual RegVal readCCRegOperand(const StaticInst *si, int idx) = 0;
192 virtual void setCCRegOperand(
193 const StaticInst *si, int idx, RegVal val) = 0;
194 /** @} */
195
196 /**
197 * @{
198 * @name Misc Register Interfaces
199 */
200 virtual RegVal readMiscRegOperand(const StaticInst *si, int idx) = 0;
201 virtual void setMiscRegOperand(const StaticInst *si,
202 int idx, RegVal val) = 0;
203
204 /**
205 * Reads a miscellaneous register, handling any architectural
206 * side effects due to reading that register.
207 */
208 virtual RegVal readMiscReg(int misc_reg) = 0;
209
210 /**
211 * Sets a miscellaneous register, handling any architectural
212 * side effects due to writing that register.
213 */
214 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
215
216 /** @} */
217
218 /**
219 * @{
220 * @name PC Control
221 */
222 virtual PCState pcState() const = 0;
223 virtual void pcState(const PCState &val) = 0;
224 /** @} */
225
226 /**
227 * @{
228 * @name Memory Interface
229 */
230 /**
231 * Perform an atomic memory read operation. Must be overridden
232 * for exec contexts that support atomic memory mode. Not pure
233 * virtual since exec contexts that only support timing memory
234 * mode need not override (though in that case this function
235 * should never be called).
236 */
237 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
238 Request::Flags flags)
239 {
240 panic("ExecContext::readMem() should be overridden\n");
241 }
242
243 /**
244 * Initiate a timing memory read operation. Must be overridden
245 * for exec contexts that support timing memory mode. Not pure
246 * virtual since exec contexts that only support atomic memory
247 * mode need not override (though in that case this function
248 * should never be called).
249 */
250 virtual Fault initiateMemRead(Addr addr, unsigned int size,
251 Request::Flags flags)
252 {
253 panic("ExecContext::initiateMemRead() should be overridden\n");
254 }
255
256 /**
257 * For atomic-mode contexts, perform an atomic memory write operation.
258 * For timing-mode contexts, initiate a timing memory write operation.
259 */
260 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
261 Request::Flags flags, uint64_t *res) = 0;
262
263 /**
|