1/*
2 * Copyright (c) 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 61 unchanged lines hidden (view full) ---

72 */
73class ExecContext {
74 public:
75 typedef TheISA::PCState PCState;
76
77 typedef TheISA::CCReg CCReg;
78 using VecRegContainer = TheISA::VecRegContainer;
79 using VecElem = TheISA::VecElem;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces
85 *
86 */
87

--- 75 unchanged lines hidden (view full) ---

163 virtual VecElem readVecElemOperand(const StaticInst *si,
164 int idx) const = 0;
165
166 /** Sets a vector register to a value. */
167 virtual void setVecElemOperand(const StaticInst *si, int idx,
168 const VecElem val) = 0;
169 /** @} */
170
171 /**
172 * @{
173 * @name Condition Code Registers
174 */
175 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
176 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
177 /** @} */
178

--- 155 unchanged lines hidden ---