1/*
2 * Copyright (c) 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::IntReg IntReg;
76 typedef TheISA::PCState PCState;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 typedef TheISA::MiscReg MiscReg;
80
81 typedef TheISA::CCReg CCReg;
82 using VecRegContainer = TheISA::VecRegContainer;
83 using VecElem = TheISA::VecElem;
84
85 public:
86 /**
87 * @{
88 * @name Integer Register Interfaces
89 *
90 */
91
92 /** Reads an integer register. */
93 virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
94
95 /** Sets an integer register to a value. */
96 virtual void setIntRegOperand(const StaticInst *si,
97 int idx, IntReg val) = 0;
98
99 /** @} */
100
101
102 /**
103 * @{
104 * @name Floating Point Register Interfaces
105 */
106
107 /** Reads a floating point register in its binary format, instead
108 * of by value. */
109 virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
110 int idx) = 0;
111
112 /** Sets the bits of a floating point register of single width
113 * to a binary value. */
114 virtual void setFloatRegOperandBits(const StaticInst *si,
115 int idx, FloatRegBits val) = 0;
116
117 /** @} */
118
119 /** Vector Register Interfaces. */
120 /** @{ */
121 /** Reads source vector register operand. */
122 virtual const VecRegContainer&
123 readVecRegOperand(const StaticInst *si, int idx) const = 0;

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180 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
181 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
182 /** @} */
183
184 /**
185 * @{
186 * @name Misc Register Interfaces
187 */
188 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
189 virtual void setMiscRegOperand(const StaticInst *si,
190 int idx, const MiscReg &val) = 0;
191
192 /**
193 * Reads a miscellaneous register, handling any architectural
194 * side effects due to reading that register.
195 */
196 virtual MiscReg readMiscReg(int misc_reg) = 0;
197
198 /**
199 * Sets a miscellaneous register, handling any architectural
200 * side effects due to writing that register.
201 */
202 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
203
204 /** @} */
205
206 /**
207 * @{
208 * @name PC Control
209 */
210 virtual PCState pcState() const = 0;

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321 /** @} */
322
323 /**
324 * @{
325 * @name MIPS-Specific Interfaces
326 */
327
328#if THE_ISA == MIPS_ISA
329 virtual MiscReg readRegOtherThread(const RegId& reg,
330 ThreadID tid = InvalidThreadID) = 0;
331 virtual void setRegOtherThread(const RegId& reg, MiscReg val,
332 ThreadID tid = InvalidThreadID) = 0;
333#endif
334
335 /** @} */
336};
337
338#endif // __CPU_EXEC_CONTEXT_HH__