1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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71 public:
72 typedef TheISA::IntReg IntReg;
73 typedef TheISA::PCState PCState;
74 typedef TheISA::FloatReg FloatReg;
75 typedef TheISA::FloatRegBits FloatRegBits;
76 typedef TheISA::MiscReg MiscReg;
77
78 typedef TheISA::CCReg CCReg;
79 typedef TheISA::VectorReg VectorReg;
80
81 public:
82 /**
83 * @{
84 * @name Integer Register Interfaces
85 *
86 */
87

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124 * @name Condition Code Registers
125 */
126 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
127 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
128 /** @} */
129
130 /**
131 * @{
132 * @name Vector Register Interfaces
133 *
134 */
135
136 /** Reads a vector register. */
137 virtual const VectorReg &readVectorRegOperand (const StaticInst *si,
138 int idx) = 0;
139
140 /** Sets a vector register to a value. */
141 virtual void setVectorRegOperand(const StaticInst *si,
142 int idx, const VectorReg &val) = 0;
143
144 /** @} */
145
146 /**
147 * @{
148 * @name Misc Register Interfaces
149 */
150 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
151 virtual void setMiscRegOperand(const StaticInst *si,
152 int idx, const MiscReg &val) = 0;
153
154 /**
155 * Reads a miscellaneous register, handling any architectural

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