1/*
2 * Copyright (c) 2014, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Andreas Sandberg
43 */
44
45#ifndef __CPU_EXEC_CONTEXT_HH__
46#define __CPU_EXEC_CONTEXT_HH__
47
48#include "arch/registers.hh"
49#include "base/types.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/reg_class.hh"
53#include "cpu/static_inst_fwd.hh"
54#include "cpu/translation.hh"
55#include "mem/request.hh"
56
57/**
58 * The ExecContext is an abstract base class the provides the
59 * interface used by the ISA to manipulate the state of the CPU model.
60 *
61 * Register accessor methods in this class typically provide the index
62 * of the instruction's operand (e.g., 0 or 1), not the architectural
63 * register index, to simplify the implementation of register
64 * renaming. The architectural register index can be found by
65 * indexing into the instruction's own operand index table.
66 *
67 * @note The methods in this class typically take a raw pointer to the
68 * StaticInst is provided instead of a ref-counted StaticInstPtr to
69 * reduce overhead as an argument. This is fine as long as the
70 * implementation doesn't copy the pointer into any long-term storage
71 * (which is pretty hard to imagine they would have reason to do).
72 */
73class ExecContext {
74 public:
75 typedef TheISA::IntReg IntReg;
76 typedef TheISA::PCState PCState;
77 typedef TheISA::FloatReg FloatReg;
78 typedef TheISA::FloatRegBits FloatRegBits;
79 typedef TheISA::MiscReg MiscReg;
80
81 typedef TheISA::CCReg CCReg;
82 using VecRegContainer = TheISA::VecRegContainer;
83 using VecElem = TheISA::VecElem;
84
85 public:
86 /**
87 * @{
88 * @name Integer Register Interfaces
89 *
90 */
91
92 /** Reads an integer register. */
93 virtual IntReg readIntRegOperand(const StaticInst *si, int idx) = 0;
94
95 /** Sets an integer register to a value. */
96 virtual void setIntRegOperand(const StaticInst *si,
97 int idx, IntReg val) = 0;
98
99 /** @} */
100
101
102 /**
103 * @{
104 * @name Floating Point Register Interfaces
105 */
106
107 /** Reads a floating point register of single register width. */
108 virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
109
110 /** Reads a floating point register in its binary format, instead
111 * of by value. */
112 virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
113 int idx) = 0;
114
115 /** Sets a floating point register of single width to a value. */
116 virtual void setFloatRegOperand(const StaticInst *si,
117 int idx, FloatReg val) = 0;
118
119 /** Sets the bits of a floating point register of single width
120 * to a binary value. */
121 virtual void setFloatRegOperandBits(const StaticInst *si,
122 int idx, FloatRegBits val) = 0;
123
124 /** @} */
125
126 /** Vector Register Interfaces. */
127 /** @{ */
128 /** Reads source vector register operand. */
129 virtual const VecRegContainer&
130 readVecRegOperand(const StaticInst *si, int idx) const = 0;
131
132 /** Gets destination vector register operand for modification. */
133 virtual VecRegContainer&
134 getWritableVecRegOperand(const StaticInst *si, int idx) = 0;
135
136 /** Sets a destination vector register operand to a value. */
137 virtual void
138 setVecRegOperand(const StaticInst *si, int idx,
139 const VecRegContainer& val) = 0;
140 /** @} */
141
142 /** Vector Register Lane Interfaces. */
143 /** @{ */
144 /** Reads source vector 8bit operand. */
145 virtual ConstVecLane8
146 readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0;
147
148 /** Reads source vector 16bit operand. */
149 virtual ConstVecLane16
150 readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0;
151
152 /** Reads source vector 32bit operand. */
153 virtual ConstVecLane32
154 readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0;
155
156 /** Reads source vector 64bit operand. */
157 virtual ConstVecLane64
158 readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0;
159
160 /** Write a lane of the destination vector operand. */
161 /** @{ */
162 virtual void setVecLaneOperand(const StaticInst *si, int idx,
163 const LaneData<LaneSize::Byte>& val) = 0;
164 virtual void setVecLaneOperand(const StaticInst *si, int idx,
165 const LaneData<LaneSize::TwoByte>& val) = 0;
166 virtual void setVecLaneOperand(const StaticInst *si, int idx,
167 const LaneData<LaneSize::FourByte>& val) = 0;
168 virtual void setVecLaneOperand(const StaticInst *si, int idx,
169 const LaneData<LaneSize::EightByte>& val) = 0;
170 /** @} */
171
172 /** Vector Elem Interfaces. */
173 /** @{ */
174 /** Reads an element of a vector register. */
175 virtual VecElem readVecElemOperand(const StaticInst *si,
176 int idx) const = 0;
177
178 /** Sets a vector register to a value. */
179 virtual void setVecElemOperand(const StaticInst *si, int idx,
180 const VecElem val) = 0;
181 /** @} */
182
183 /**
184 * @{
185 * @name Condition Code Registers
186 */
187 virtual CCReg readCCRegOperand(const StaticInst *si, int idx) = 0;
188 virtual void setCCRegOperand(const StaticInst *si, int idx, CCReg val) = 0;
189 /** @} */
190
191 /**
192 * @{
193 * @name Misc Register Interfaces
194 */
195 virtual MiscReg readMiscRegOperand(const StaticInst *si, int idx) = 0;
196 virtual void setMiscRegOperand(const StaticInst *si,
197 int idx, const MiscReg &val) = 0;
198
199 /**
200 * Reads a miscellaneous register, handling any architectural
201 * side effects due to reading that register.
202 */
203 virtual MiscReg readMiscReg(int misc_reg) = 0;
204
205 /**
206 * Sets a miscellaneous register, handling any architectural
207 * side effects due to writing that register.
208 */
209 virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
210
211 /** @} */
212
213 /**
214 * @{
215 * @name PC Control
216 */
217 virtual PCState pcState() const = 0;
218 virtual void pcState(const PCState &val) = 0;
219 /** @} */
220
221 /**
222 * @{
223 * @name Memory Interface
224 */
225 /**
226 * Perform an atomic memory read operation. Must be overridden
227 * for exec contexts that support atomic memory mode. Not pure
228 * virtual since exec contexts that only support timing memory
229 * mode need not override (though in that case this function
230 * should never be called).
231 */
232 virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size,
233 Request::Flags flags)
234 {
235 panic("ExecContext::readMem() should be overridden\n");
236 }
237
238 /**
239 * Initiate a timing memory read operation. Must be overridden
240 * for exec contexts that support timing memory mode. Not pure
241 * virtual since exec contexts that only support atomic memory
242 * mode need not override (though in that case this function
243 * should never be called).
244 */
245 virtual Fault initiateMemRead(Addr addr, unsigned int size,
246 Request::Flags flags)
247 {
248 panic("ExecContext::initiateMemRead() should be overridden\n");
249 }
250
251 /**
252 * For atomic-mode contexts, perform an atomic memory write operation.
253 * For timing-mode contexts, initiate a timing memory write operation.
254 */
255 virtual Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
256 Request::Flags flags, uint64_t *res) = 0;
257
258 /**
259 * Sets the number of consecutive store conditional failures.
260 */
261 virtual void setStCondFailures(unsigned int sc_failures) = 0;
262
263 /**
264 * Returns the number of consecutive store conditional failures.
265 */
266 virtual unsigned int readStCondFailures() const = 0;
267
268 /** @} */
269
270 /**
271 * @{
272 * @name SysCall Emulation Interfaces
273 */
274
275 /**
276 * Executes a syscall specified by the callnum.
277 */
278 virtual void syscall(int64_t callnum, Fault *fault) = 0;
279
280 /** @} */
281
282 /** Returns a pointer to the ThreadContext. */
283 virtual ThreadContext *tcBase() = 0;
284
285 /**
286 * @{
287 * @name Alpha-Specific Interfaces
288 */
289
290 /**
291 * Somewhat Alpha-specific function that handles returning from an
292 * error or interrupt.
293 */
294 virtual Fault hwrei() = 0;
295
296 /**
297 * Check for special simulator handling of specific PAL calls. If
298 * return value is false, actual PAL call will be suppressed.
299 */
300 virtual bool simPalCheck(int palFunc) = 0;
301
302 /** @} */
303
304 /**
305 * @{
306 * @name ARM-Specific Interfaces
307 */
308
309 virtual bool readPredicate() const = 0;
310 virtual void setPredicate(bool val) = 0;
311
312 /** @} */
313
314 /**
315 * @{
316 * @name X86-Specific Interfaces
317 */
318
319 /**
320 * Invalidate a page in the DTLB <i>and</i> ITLB.
321 */
322 virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
323 virtual void armMonitor(Addr address) = 0;
324 virtual bool mwait(PacketPtr pkt) = 0;
325 virtual void mwaitAtomic(ThreadContext *tc) = 0;
326 virtual AddressMonitor *getAddrMonitor() = 0;
327
328 /** @} */
329
330 /**
331 * @{
332 * @name MIPS-Specific Interfaces
333 */
334
335#if THE_ISA == MIPS_ISA
336 virtual MiscReg readRegOtherThread(const RegId& reg,
337 ThreadID tid = InvalidThreadID) = 0;
338 virtual void setRegOtherThread(const RegId& reg, MiscReg val,
339 ThreadID tid = InvalidThreadID) = 0;
340#endif
341
342 /** @} */
343};
344
345#endif // __CPU_EXEC_CONTEXT_HH__